公开(公告)号：US08786093B2

公开(公告)日：2014-07-22

申请号：US13359452

申请日：2012-01-26

申请人： Chia-Sheng Lin ,  Tzu-Hsiang Hung

发明人： Chia-Sheng Lin ,  Tzu-Hsiang Hung

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/60 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/522 ,  H01L23/60 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：衬底; 设置在所述基板中或所述基板上的器件区域; 信号焊盘，设置在所述衬底中或所述衬底上并电连接到所述器件区域; 设置在基板中或基板上的接地焊盘; 设置在所述基板的表面上的信号凸起，其中所述信号凸起通过信号传导层电连接到所述信号焊盘; 接地导电层，设置在所述基板的表面上并电连接到所述接地垫; 以及设置在基板的表面上的保护层，其中保护层完全覆盖信号传导层的整个侧面端子并且部分地覆盖接地导电层，使得接地导电层的侧端子暴露在 底物。

公开(公告)号：US08779557B2

公开(公告)日：2014-07-15

申请号：US13476748

申请日：2012-05-21

申请人： Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Po-Shen Lin

发明人： Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Po-Shen Lin

IPC分类号： H01L21/78 ,  H01L21/68 ,  H01L23/544

CPC分类号： H01L21/78 ,  H01L21/682 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：衬底，其中所述衬底从晶片切割; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及形成在所述绝缘层上的材料层，其中所述材料层具有识别标记，并且所述识别标记在从所述晶片切割所述基板之前，示出所述晶片中的所述基板的位置信息。

公开(公告)号：US20110103155A1

公开(公告)日：2011-05-05

申请号：US12841739

申请日：2010-07-22

申请人： Ting-Chang Chang ,  Te-Chih Chen ,  Fu-Yen Jian ,  Chia-Sheng Lin

发明人： Ting-Chang Chang ,  Te-Chih Chen ,  Fu-Yen Jian ,  Chia-Sheng Lin

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.

摘要翻译： 本发明的一个实施例提供一种存储装置的操作方法。 存储器件包括源极和漏极之间的源极，漏极和沟道区域，在沟道区域上具有电荷存储层的栅极电介质和栅极电介质上的栅极，其中源极，漏极和漏极 沟道区域位于衬底中。 操作方法包括以下步骤：在存储器件的栅极和漏极之间施加反向偏置，以在漏极附近的衬底中产生带对带热孔; 将带 - 带热孔注入到电荷存储层的漏极侧; 以及对存储器件执行编程/擦除操作。 通过编程/擦除操作，电荷存储层的漏极侧的带对带热孔并不完全消失。

公开(公告)号：US06609275B1

公开(公告)日：2003-08-26

申请号：US10062763

申请日：2002-02-05

申请人： Chia-Sheng Lin

发明人： Chia-Sheng Lin

IPC分类号： A44B2100

CPC分类号： B60P7/0846 ,  B60P7/0823 ,  B60P7/083 ,  Y10S24/909 ,  Y10T24/2147 ,  Y10T24/2175 ,  Y10T24/2177

摘要： A strap tightener has an auto-pulling device connected to a seat. The auto-pulling device includes a housing and a reversing device. The reversing device is rotatably received in the housing. The reversing device has a reel received in the housing to connect with one end of a strap. A spiral power spring is connected between the housing and the reel. Consequently, the strap can be automatically wound around the reel after the strap tightener is used. To collect the strap is convenient and the operating time of collecting the strap is saved.

摘要翻译： 带子拉紧器具有连接到座椅的自动牵引装置。 自动牵引装置包括壳体和换向装置。 反转装置可旋转地容纳在壳体中。 反转装置具有容纳在壳体中以与带的一端连接的卷轴。 螺旋动力弹簧连接在外壳和卷轴之间。 因此，在使用吊带拉紧器之后，带可以自动地卷绕在卷轴上。 收集表带方便，节省了收集皮带的操作时间。

公开(公告)号：US08952519B2

公开(公告)日：2015-02-10

申请号：US12816301

申请日：2010-06-15

申请人： Chia-Sheng Lin ,  Po-Han Lee

发明人： Chia-Sheng Lin ,  Po-Han Lee

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L21/76898 ,  H01L21/481 ,  H01L21/76897 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00

摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

摘要翻译： 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。 形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。 然后，保护层设置在半导体衬底的第一表面和凹部中。

公开(公告)号：US08742564B2

公开(公告)日：2014-06-03

申请号：US13350520

申请日：2012-01-13

申请人： Bai-Yao Lou ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Tzu-Hsiang Hung

发明人： Bai-Yao Lou ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Tzu-Hsiang Hung

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/73153 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

公开(公告)号：US20110169139A1

公开(公告)日：2011-07-14

申请号：US12687093

申请日：2010-01-13

申请人： Chia-Sheng Lin ,  Chia-Lun Tsai ,  Chang-Sheng Hsu ,  Po-Han Lee

发明人： Chia-Sheng Lin ,  Chia-Lun Tsai ,  Chang-Sheng Hsu ,  Po-Han Lee

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L24/73 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/29 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.

摘要翻译： 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 在第一表面上形成有从第一表面延伸到第二表面的通孔。 导电迹线层形成在第一表面和通孔中。 在通孔中形成缓冲塞，在第一表面和通孔中形成保护层。

公开(公告)号：US06669418B1

公开(公告)日：2003-12-30

申请号：US10162346

申请日：2002-06-05

申请人： Chia-Sheng Lin

发明人： Chia-Sheng Lin

IPC分类号： B60P708

CPC分类号： B60P7/0807

摘要： A device is mounted in the deck of a truck for catching a cargo-locating rope and is formed of a base, a top plate, and a rope-catching plate. The base is mounted in a mounting hole of the deck. The top plate is fastened with the top of the base. The rope-catching plate is slidably located in a receiving slot of the base such that the locating balls of the rope-catching plate are retained in first locating recesses of guide grooves of the base at the time when the rope-catching plate is pulled out of the base to catch the cargo-locating rope. When the rope-catching plate is pushed back into the base, the locating balls of the rope-catching plate move along the guide grooves to locate in second locating recesses of the guide grooves.

摘要翻译： 一种装置安装在卡车的甲板上，用于捕捉货物定位绳索，并由基座，顶板和绳索捕捉板形成。 基座安装在甲板的安装孔中。 顶板用底座的顶部固定。 牵引板可滑动地位于基座的接收槽中，使得牵引板的定位球在拉出绳索卡扣时保持在基座的引导槽的第一定位凹槽中 的基地抓住货物定位绳。 当将抓绳板推回到基座中时，绳索捕捉板的定位球沿着引导槽移动以定位在引导槽的第二定位凹槽中。

公开(公告)号：US08901701B2

公开(公告)日：2014-12-02

申请号：US13369085

申请日：2012-02-08

申请人： Chia-Sheng Lin

发明人： Chia-Sheng Lin

IPC分类号： H01L21/70 ,  H01L21/76 ,  H01L21/768 ,  H01L23/525 ,  H01L23/31 ,  H01L23/48 ,  H01L27/146 ,  H01L23/00

CPC分类号： H01L31/02005 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02327 ,  H01L31/1876 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00

摘要： A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

摘要翻译： 公开了一种芯片封装。 所述封装包括具有第一表面和与其相对的第二表面的半导体芯片，与所述第一表面相邻的至少一个导电焊盘以及从所述第二表面向所述第一表面延伸以露出所述导电焊盘的开口。 与第一表面相邻的口径大于与第二表面相邻的开口的口径。 绝缘层和再分配层（RDL）依次设置在第二表面上并延伸到开口的侧壁和底部，RDL通过开口与导电焊盘电连接。 钝化层覆盖RDL并且部分填充开口以在开口中的钝化层和导电垫之间形成空隙。 还公开了芯片封装的制造方法。

公开(公告)号：US08878367B2

公开(公告)日：2014-11-04

申请号：US13303208

申请日：2011-11-23

申请人： Chia-Sheng Lin ,  Chien-Hui Chen ,  Bing-Siang Chen ,  Tzu-Hsiang Hung

发明人： Chia-Sheng Lin ,  Chien-Hui Chen ,  Bing-Siang Chen ,  Tzu-Hsiang Hung

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76898 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.

摘要翻译： 提供具有通孔的衬底结构。 具有贯通孔的衬底结构包括具有后表面和穿过背面的通孔的半导体衬底，金属层，第一绝缘层和第二绝缘层。 第一绝缘层形成在半导体衬底的后表面上，并且具有连接到通孔的开口。 第二绝缘层形成在第一绝缘层上，并且具有延伸到开口中的部分和通孔以形成沟槽绝缘层。 沟槽绝缘层的底部被回蚀以在通孔的拐角处形成基部。 所述基脚部分的高度小于所述第一和第二绝缘层的总高度。