公开(公告)号：US20130328064A1

公开(公告)日：2013-12-12

申请号：US13967886

申请日：2013-08-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Avinash Srikrishnan Kashyap ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Peter Micah Sandvik ,  Stephen Daley Arthur ,  Vinayak Tilak

IPC: H01L21/56 ,  H01L29/16

CPC classification number: H01L21/56 ,  H01L23/3185 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

Abstract translation: 提供了形成碳化硅瞬态电压抑制器（TVS）组件的方法和用于瞬态电压抑制器（TVS）组件的系统。 TVS组件包括台面结构中的半导体管芯，其包括具有第一极性的导电率的第一宽带隙半导体的第一层，具有第二极导电率的第一或第二宽带隙半导体的第二层 极性与第一层电接触，其中第二极性不同于第一极性。 TVS组件还包括具有与第二层电接触的第一极性的导电性的第一，第二或第三宽带隙半导体的第三层。 相对于具有第一极性的导电性的层，具有第二极性的导电性的层被轻掺杂。

公开(公告)号：US10103540B2

公开(公告)日：2018-10-16

申请号：US14261195

申请日：2014-04-24

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Joe Walter Kirstein ,  Alexander Viktorovich Bolotnikov

IPC: H02H9/04 ,  H01L21/02 ,  H01L21/768 ,  H01L25/00 ,  H01L29/16 ,  H01L27/02 ,  H01L25/065 ,  H01L29/70 ,  G01R31/28 ,  G01R1/04 ,  G01R31/26 ,  H01L29/423 ,  H01L29/732

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

公开(公告)号：US09508841B2

公开(公告)日：2016-11-29

申请号：US13957115

申请日：2013-08-01

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/74 ,  H01L27/02 ,  H01L29/861 ,  H01L29/739

CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract translation: 提供功率晶体管组件和操作组件的方法。 所述功率晶体管组件包括在单个半导体衬底上的集成瞬态电压抑制，并且包括由宽带隙材料形成的晶体管，所述晶体管包括栅极端子，源极端子和漏极端子，所述晶体管还包括预定的最大允许量 栅极电压值以及由宽带隙材料形成的瞬态电压抑制（TVS）器件，所述TVS器件由所述晶体管形成为单个半导体器件，所述TVS器件电耦合到所述晶体管的至少一个栅极和 源极端子和漏极和源极端子，TVS器件包括被选择为大于预定的最大允许栅极电压值的击穿电压限制。

公开(公告)号：US20150034969A1

公开(公告)日：2015-02-05

申请号：US13957115

申请日：2013-08-01

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/06 ,  H01L29/74 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract translation: 提供功率晶体管组件和操作组件的方法。 所述功率晶体管组件包括在单个半导体衬底上的集成瞬态电压抑制，并且包括由宽带隙材料形成的晶体管，所述晶体管包括栅极端子，源极端子和漏极端子，所述晶体管还包括预定的最大允许量 栅极电压值以及由宽带隙材料形成的瞬态电压抑制（TVS）器件，所述TVS器件由所述晶体管形成为单个半导体器件，所述TVS器件电耦合到所述晶体管的至少一个栅极和 源极端子和漏极和源极端子，TVS器件包括被选择为大于预定的最大允许栅极电压值的击穿电压限制。

公开(公告)号：US20140264775A1

公开(公告)日：2014-09-18

申请号：US13846380

申请日：2013-03-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Stephen Daley Arthur

IPC: H01L29/06 ,  H01L21/265

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/8618 ,  H01L2924/10272

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract translation: 提供瞬态电压抑制（TVS）装置和形成装置的方法。 该器件包括由第一导电类型材料形成的第一层宽带隙半导体材料，在第一层的至少一部分上由第二导电类型材料形成的第二层宽带隙半导体材料，并且包括离子注入 材料结构在0.1微米（μm）和22.0μm厚之间，第二层使用穿透物理学操作，以及在第二层的至少一部分上由第一导电类型材料形成的第三层宽带隙半导体材料。

公开(公告)号：US08765524B2

公开(公告)日：2014-07-01

申请号：US13967886

申请日：2013-08-15

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Peter Micah Sandvik ,  Stephen Daley Arthur ,  Vinayak Tilak

IPC: H01L21/00

CPC classification number: H01L21/56 ,  H01L23/3185 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

Abstract translation: 提供了形成碳化硅瞬态电压抑制器（TVS）组件的方法和用于瞬态电压抑制器（TVS）组件的系统。 TVS组件包括台面结构中的半导体管芯，其包括具有第一极性的导电率的第一宽带隙半导体的第一层，具有第二极导电率的第一或第二宽带隙半导体的第二层 极性与第一层电接触，其中第二极性不同于第一极性。 TVS组件还包括具有与第二层电接触的第一极性的导电性的第一，第二或第三宽带隙半导体的第三层。 相对于具有第一极性的导电性的层，具有第二极性的导电性的层被轻掺杂。

公开(公告)号：US10186509B2

公开(公告)日：2019-01-22

申请号：US15333868

申请日：2016-10-25

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/74 ,  H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L29/861 ,  H01L29/739

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

公开(公告)号：US10014388B1

公开(公告)日：2018-07-03

申请号：US15398489

申请日：2017-01-04

Applicant: General Electric Company

Inventor： Victor Mario Torres ,  Reza Ghandi ,  David Alan Lilienfeld ,  Avinash Srikrishnan Kashyap ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/74 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/861 ,  H01L29/78

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

公开(公告)号：US09947647B2

公开(公告)日：2018-04-17

申请号：US14102632

申请日：2013-12-11

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Mark Gerard Roberto ,  David Mulford Shaddock ,  Joe Walter Kirstein

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H02H9/041 ,  Y10T29/49117

Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.

公开(公告)号：US09130365B2

公开(公告)日：2015-09-08

申请号：US14486138

申请日：2014-09-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Avinash Srikrishnan Kashyap ,  Emad Andarawis Andarawis ,  David Mulford Shaddock

IPC: H01L29/66 ,  H01L21/332 ,  H02H1/04 ,  H01L21/50 ,  H01L29/861 ,  H01L21/82 ,  H01L27/06 ,  H01L27/08 ,  H01L27/02 ,  H01L23/00 ,  H02H3/20 ,  H01L29/45 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8252

CPC classification number: H02H1/04 ,  H01L21/50 ,  H01L21/8213 ,  H01L21/8252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0814 ,  H01L29/0661 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/861 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13109 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2924/10272 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/15192 ,  H01L2924/3025 ,  H02H3/20 ,  H01L2924/0105 ,  H01L2924/00

Abstract: A high temperature electronic system includes an electronics unit configured for exposure to an environment having a temperature greater than approximately 150.0° C. The remote electronics unit includes a transient voltage suppressor (TVS) assembly coupled in operative relationship with at least some electronic components of the electronics unit. The TVS assembly includes at least one TVS device comprising at least one of a punch-through wide band-gap semiconductor TVS die and an avalanche breakdown wide band-gap semiconductor TVS die encapsulated in a flip-chip package at least partially surrounding the die, and coupled to first and second electrodes exposed to a single side of the encapsulation.

Abstract translation: 高温电子系统包括被配置为暴露于温度大于约150.0℃的环境的电子单元。远程电子单元包括瞬态电压抑制器（TVS）组件，其与至少一些电子部件的操作关系耦合 电子单元。 TVS组件包括至少一个TVS装置，其包括穿透宽带隙半导体TVS管芯和封装在至少部分围绕管芯的倒装芯片封装的雪崩击穿宽带隙半导体TVS管芯中的至少一个， 并且耦合到暴露于封装的单侧的第一和第二电极。