公开(公告)号：US10403711B2

公开(公告)日：2019-09-03

申请号：US15295779

申请日：2016-10-17

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Ljubisa Dragoljub Stevanovic ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/732 ,  H01L29/808 ,  H01L29/78 ,  H01L29/745 ,  H01L29/739 ,  H01L29/66 ,  G06F17/50 ,  H01L29/16 ,  H01L23/556 ,  H01L23/552 ,  H01L29/872 ,  H01L29/868

Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.

公开(公告)号：US10347608B2

公开(公告)日：2019-07-09

申请号：US15605686

申请日：2017-05-25

Applicant: General Electric Company

Inventor： Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic

IPC: H01L25/07 ,  H01L29/16 ,  H02M7/00 ,  H01L23/64

Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.

公开(公告)号：US10186509B2

公开(公告)日：2019-01-22

申请号：US15333868

申请日：2016-10-25

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/74 ,  H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L29/861 ,  H01L29/739

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

公开(公告)号：US09899512B2

公开(公告)日：2018-02-20

申请号：US15052664

申请日：2016-02-24

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Ljubisa Dragoljub Stevanovic ,  Gregory Thomas Dunne ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/7395 ,  H01L29/745 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8083

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm−2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

公开(公告)号：US20170243935A1

公开(公告)日：2017-08-24

申请号：US15295779

申请日：2016-10-17

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Ljubisa Dragoljub Stevanovic ,  Peter Almern Losee

IPC: H01L29/06 ,  G06F17/50 ,  H01L23/556 ,  H01L29/16 ,  H01L23/552

CPC classification number: H01L29/06 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/06 ,  H01L23/552 ,  H01L23/556 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/745 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.

公开(公告)号：US09406762B2

公开(公告)日：2016-08-02

申请号：US14396852

申请日：2013-05-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract translation: 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。

公开(公告)号：US20180212512A1

公开(公告)日：2018-07-26

申请号：US15411422

申请日：2017-01-20

Applicant: General Electric Company

Inventor： Ravisekhar Nadimpalli Raju ,  Ramanujam Ramabhadran ,  Ljubisa Dragoljub Stevanovic ,  William George Earls

IPC: H02M1/32 ,  H02M1/08 ,  H02M7/217

CPC classification number: H02M1/32 ,  H02M7/217

Abstract: Systems and methods for providing automatic short circuit protection in an electrical system via a switching device. In some embodiments, the switching device includes a switching transistor that selectively switches between an open position and a closed position based at least in part on a switching control signal, for example, to facilitate converting electrical power with first electrical characteristics output into electrical power with the second electrical characteristics. Additionally, the switching device includes a protection transistor electrically coupled in series with the switching transistor, in which a constant gate voltage is supplied to the protection transistor to maintain the first protection transistor in the closed position during operation of the power converter; and the protection transistor automatically limits current flow through the first switching device by reducing a gate voltage applied to the switching transistor when a short circuit is expected to be present in the electrical system.

公开(公告)号：US09972569B2

公开(公告)日：2018-05-15

申请号：US15482228

申请日：2017-04-07

Applicant: General Electric Company

Inventor： Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/49 ,  H01L23/492 ,  H01L23/495 ,  H01L23/50 ,  H01L25/00 ,  H01L25/18 ,  H01L25/07

CPC classification number: H01L23/50 ,  H01L23/142 ,  H01L23/49 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2224/45099

Abstract: A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.

公开(公告)号：US20180123476A1

公开(公告)日：2018-05-03

申请号：US15336413

申请日：2016-10-27

Applicant: General Electric Company

Inventor： Michael Joseph Schutten ,  Fengfeng Tao ,  Maja Harfman-Todorovic ,  Ravisekhar Nadimpalli Raju ,  Philip Michael Cioffi ,  Ljubisa Dragoljub Stevanovic

IPC: H02M7/537 ,  H05K3/30 ,  H05K3/36

CPC classification number: H02M7/537 ,  H05K1/0218 ,  H05K1/0243 ,  H05K3/30 ,  H05K3/36

Abstract: A power module includes an input bus, a switching device, and an output bus. The input bus includes a first coating of a high permeability magnetic conductive material and is configured to receive input direct current (DC) electrical power from an electrical power source. The switching device is electrically coupled to the first input bus, and is configured to selectively connect and disconnect to facilitate converting the input DC electrical power into output alternating current (AC) electrical power. The output bus includes a second coating of the high permeability magnetic conductive material, and is electrically coupled to the first switching device. The output bus is configured to supply the output AC electrical power to an electrical load.

公开(公告)号：US09508841B2

公开(公告)日：2016-11-29

申请号：US13957115

申请日：2013-08-01

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/74 ,  H01L27/02 ,  H01L29/861 ,  H01L29/739

CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract translation: 提供功率晶体管组件和操作组件的方法。 所述功率晶体管组件包括在单个半导体衬底上的集成瞬态电压抑制，并且包括由宽带隙材料形成的晶体管，所述晶体管包括栅极端子，源极端子和漏极端子，所述晶体管还包括预定的最大允许量 栅极电压值以及由宽带隙材料形成的瞬态电压抑制（TVS）器件，所述TVS器件由所述晶体管形成为单个半导体器件，所述TVS器件电耦合到所述晶体管的至少一个栅极和 源极端子和漏极和源极端子，TVS器件包括被选择为大于预定的最大允许栅极电压值的击穿电压限制。