公开(公告)号：US20180130895A1

公开(公告)日：2018-05-10

申请号：US15345644

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US09859125B2

公开(公告)日：2018-01-02

申请号：US15072626

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Kwan-Yong Lim

IPC: H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US09685522B1

公开(公告)日：2017-06-20

申请号：US15093952

申请日：2016-04-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie ,  Chanro Park

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42392 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/775

Abstract: Methods for forming uniform WF metal layers in gate areas of NS structures in a NS FET and the resulting devices are disclosed. Embodiments include providing NS structures, parallel to and spaced from each other, in a substrate; conformally forming gate dielectric and metal layers, respectively, on all surfaces in a gate area of each NS structure; forming a barrier layer on surfaces in the gate area of each NS structure except on surfaces in between the NS structures by PVD or PECVD; annealing the NS structures including the gate dielectric and metal layers; removing the barrier and metal layers from all surfaces; and forming a WF metal layer on all surfaces in the gate area of each NS structure.

公开(公告)号：US09627535B2

公开(公告)日：2017-04-18

申请号：US15055805

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches.

公开(公告)号：US09601490B2

公开(公告)日：2017-03-21

申请号：US15040953

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Hoon Kim

IPC: H01L27/092 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795

Abstract: An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities.

公开(公告)号：US20170047253A1

公开(公告)日：2017-02-16

申请号：US14822340

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种示例性方法包括在源极/漏极区域上形成二氧化硅蚀刻停止层并与源极/漏极区域接触的相邻的氮化硅侧壁间隔物，其位于具有二氧化硅栅极盖层的两个横向间隔开的晶体管上， 通过绝缘材料层中的开口进行第一蚀刻工艺，以去除位于源/漏区域上方的氮化硅材料，执行第二蚀刻工艺以去除二氧化硅蚀刻停止层的一部分，从而暴露出源的一部分 /漏极区域，并且形成导电地与源极/漏极区域耦合的导电自对准接触。

公开(公告)号：US09496143B2

公开(公告)日：2016-11-15

申请号：US13670251

申请日：2012-11-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hoon Kim ,  Kisik Choi

IPC: H01L21/02 ,  H01L21/8222 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.

Abstract translation: 通过包括相对较厚的TiN的退火层来支配并将整个功函数从PFET的整个功能转移到底部，从而产生用于在NFET和PFET之间进行阈值电压控制的中隙工作功能的基于PFET的半导体栅极结构。 该结构具有覆盖有高k电介质层，退火TiN层，未退火TiN层，未退火TiN上的薄势垒和薄势垒上的n型金属的PFET基极。

公开(公告)号：US09461171B2

公开(公告)日：2016-10-04

申请号：US14283636

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Naim Moumen ,  Chanro Park ,  William J. Taylor, Jr.

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，执行外延沉积工艺以在器件的源极/漏极区域中的有源区上形成外延半导体材料，进行蚀刻 处理外延半导体材料以去除外延半导体材料的一部分，以便限定外延半导体材料中的至少一个外延凹部，在外延半导体材料的上表面上形成金属硅化物层，并且在至少一个 epi凹槽，并且形成导电耦合到金属硅化物层的导电结构。

公开(公告)号：US09391174B1

公开(公告)日：2016-07-12

申请号：US14730735

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/3083

Abstract: Uniform fin recessing for the situation of recessing nonadjacent fins and the situation of recessing adjacent fins includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple fins coupled to the substrate, each fin having a hard mask layer thereover and being surrounded by isolation material. The hard mask layer is then removed over some of the fins, at least partially removing the some of the raised structures, the at least partially removing creating openings, and filling the openings with an optical planarization layer (OPL) material.

Abstract translation: 针对不相邻散热片的凹陷状况的均匀的翅片凹陷以及相邻散热片的凹陷情况包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个鳍片，每个散热片具有其上的硬掩模层并被 隔离材料。 然后在一些翅片上去除硬掩模层，至少部分地去除一些凸起结构，至少部分去除创建开口，并用光学平坦化层（OPL）材料填充开口。

公开(公告)号：US09373542B2

公开(公告)日：2016-06-21

申请号：US14081749

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract translation: 提供具有改进的接触结构的集成电路和用于制造具有改进的接触结构的集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底内和/或半导体衬底上提供器件。 此外，该方法包括形成与该装置电接触的接触结构。 接触结构包括覆盖该装置的硅酸盐阻挡部分，覆盖该装置并且位于硅酸盐阻挡部分之间的阻挡金属以及覆盖该阻挡金属并位于硅酸盐阻挡部分之间的填充金属。