公开(公告)号：US09589912B1

公开(公告)日：2017-03-07

申请号：US14837737

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jim S. Liang ,  Atsushi Ogino ,  Stephen E. Greco ,  Roger A. Quon

IPC: H01L23/528 ,  H01L21/31 ,  H01L23/00 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L23/562 ,  H01L21/31144 ,  H01L23/522 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/53295

Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.

Abstract translation: 本公开的第一方面提供一种集成电路结构。 集成电路结构可以包括在裂纹停止区域中的衬底上的第一介电层中的第一金属结构; 以及在第二电介质层中的第一裂纹阻挡结构，所述第一裂纹阻挡结构在所述第一金属结构之上，并且包括：与所述第一金属结构接触的第一金属填充物; 以及基本分离第一金属填充物和第二介电层的气缝。

公开(公告)号：US20190181215A1

公开(公告)日：2019-06-13

申请号：US15834443

申请日：2017-12-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Lin Hu ,  Brian Greene

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

公开(公告)号：US09997456B2

公开(公告)日：2018-06-12

申请号：US15220764

申请日：2016-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/5286

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

公开(公告)号：US09589911B1

公开(公告)日：2017-03-07

申请号：US14837461

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jim S. Liang ,  Atsushi Ogino ,  Roger A. Quon ,  Stephen E. Greco

IPC: H01L21/14 ,  H01L21/784 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00 ,  H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/522 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/535

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.

Abstract translation: 本公开的实施例提供具有金属裂纹停止的集成电路（IC）结构及其形成方法。 根据本公开的实施例的IC结构可以包括位于衬底上的绝缘体; 位于所述绝缘体上方的阻挡膜; 位于阻挡膜上方的层间电介质; 以及金属裂纹停止件，其位于所述基板上并且横向邻近所述绝缘体，所述阻挡膜和所述层间电介质中的每一个，其中所述金属裂纹停止件包括其中具有第一凹部的侧壁，并且其中所述阻挡膜 并且层间电介质与金属裂纹停止件的侧壁相交。

公开(公告)号：US20170062354A1

公开(公告)日：2017-03-02

申请号：US14837461

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jim S. Liang ,  Atsushi Ogino ,  Roger A. Quon ,  Stephen E. Greco

IPC: H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/522 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/535

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.

Abstract translation: 本公开的实施例提供具有金属裂纹停止的集成电路（IC）结构及其形成方法。 根据本公开的实施例的IC结构可以包括位于衬底上的绝缘体; 位于所述绝缘体上方的阻挡膜; 位于阻挡膜上方的层间电介质; 以及金属裂纹停止件，其位于所述基板上并且横向邻近所述绝缘体，所述阻挡膜和所述层间电介质中的每一个，其中所述金属裂纹停止件包括其中具有第一凹部的侧壁，并且其中所述阻挡膜 并且层间电介质与金属裂纹停止件的侧壁相交。

公开(公告)号：US10790204B2

公开(公告)日：2020-09-29

申请号：US16185696

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L29/772

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

公开(公告)号：US10438890B2

公开(公告)日：2019-10-08

申请号：US15976300

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/283 ,  H01L21/28

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

公开(公告)号：US10403574B2

公开(公告)日：2019-09-03

申请号：US15820602

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jim Shih-Chun Liang ,  Atsushi Ogino ,  Justin C. Long

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

公开(公告)号：US10229918B2

公开(公告)日：2019-03-12

申请号：US15662594

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino

IPC: H01L27/11 ,  H01L21/308 ,  H01L21/318 ,  H01L21/033 ,  H01L27/02 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.

公开(公告)号：US20180033718A1

公开(公告)日：2018-02-01

申请号：US15220764

申请日：2016-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/528 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/5286

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.