公开(公告)号：US09431528B2

公开(公告)日：2016-08-30

申请号：US14281359

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xiang Hu ,  Zhao Lun ,  Huang Liu

IPC: H01L21/311 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/0684 ,  H01L29/12 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract translation: 诸如FinFET的非平面半导体结构的凸起结构（例如，翅片）上的光刻叠层包括旋涂非晶碳或旋涂有机平面化材料的底层，氮化物的硬掩模层 和/或旋涂层上的氧化物，硬掩模层上的可显影底部抗反射涂层（dBARC）的层和光致抗蚀剂的顶层。 蚀刻该叠层以露出和凹进凸起的结构，并且外延结构在凹槽上生长。

公开(公告)号：US09419101B1

公开(公告)日：2016-08-16

申请号：US14932394

申请日：2015-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Zhao Lun ,  Tao Han ,  Hsien-Ching Lo ,  Basab Banerjee ,  Wen Zhi Gao ,  Byoung-Gi Min

IPC: H01L21/8232 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.

Abstract translation: 提供了形成间隔物的方法和所得的鳍状场效应晶体管。 实施例包括在衬底上形成硅（Si）鳍; 在Si鳍上形成多晶硅栅极; 以及在所述多晶硅栅极的顶表面和侧表面上形成间隔物，并且在所述Si鳍的暴露的上表面和外表面上，所述间隔物包括：具有第一介电常数的第一层和第二层，以及形成在所述第一 和第二层并具有第二介电常数，其中第二介电常数低于第一介电常数。

公开(公告)号：US20150380515A1

公开(公告)日：2015-12-31

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。

公开(公告)号：US20150380502A1

公开(公告)日：2015-12-31

申请号：US14849335

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jinping Liu

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

公开(公告)号：US20200287019A1

公开(公告)日：2020-09-10

申请号：US16296769

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Hong Yu ,  Man Gu ,  Jianwei Peng ,  Michael Aquilino

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US20200243643A1

公开(公告)日：2020-07-30

申请号：US16256252

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.

公开(公告)号：US10566202B1

公开(公告)日：2020-02-18

申请号：US16203623

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Hong Yu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423

Abstract: A method of fabricating a semiconductor device is provided, including providing sacrificial gate structures over a plurality of fins. The sacrificial gate structures include a sacrificial first gate structure and a sacrificial second gate structure. A first gate cut process is performed to form a first gate cut opening in the sacrificial first gate structure, and a second gate cut opening in the sacrificial second gate structure. A first dielectric layer is deposited in the first gate cut opening and the second gate cut opening. The first dielectric layer completely fills the first gate cut opening and partially fills the second gate cut opening. The first dielectric layer is removed from the second gate cut opening, and a second gate cut process is performed. A second dielectric layer is deposited in the second gate cut opening to form a gate cut structure.

公开(公告)号：US10559470B2

公开(公告)日：2020-02-11

申请号：US15876407

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinsheng Gao ,  Hong Yu ,  Jinping Liu ,  Huang Liu

IPC: H01L27/08 ,  H01L21/28 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

公开(公告)号：US10446683B2

公开(公告)日：2019-10-15

申请号：US15702278

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Hong Yu

IPC: H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice. A fin is formed on a semiconductor substrate. A gate region is formed over the fin. In a source region and a drain region adjacent bottom portions of the fin, a first recess cavity is formed in the source region, and a second recess cavity is formed in the drain region. The first and second recess cavities comprise sidewalls formed in an angle relative to a vertical axis. Portions of the first and second recess cavities extend below the fin. In the first recess cavity, a first rare earth oxide layer is formed, and in the second recess cavity, a second rare earth oxide layer is formed.

公开(公告)号：US20190312117A1

公开(公告)日：2019-10-10

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.