公开(公告)号：US09876077B1

公开(公告)日：2018-01-23

申请号：US15197944

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.

公开(公告)号：US09875940B2

公开(公告)日：2018-01-23

申请号：US14820701

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

公开(公告)号：US09831132B2

公开(公告)日：2017-11-28

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US09824920B2

公开(公告)日：2017-11-21

申请号：US15089834

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.

公开(公告)号：US09779987B2

公开(公告)日：2017-10-03

申请号：US14314670

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Kwanyong Lim ,  Hiroaki Niimi

IPC: H01L21/768 ,  H01L23/485 ,  H01L21/285 ,  H01L29/417 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

公开(公告)号：US09761495B1

公开(公告)日：2017-09-12

申请号：US15050540

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

公开(公告)号：US09735060B1

公开(公告)日：2017-08-15

申请号：US15006304

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L21/302 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/823481

Abstract: For an integrated circuit product comprising a non-tapered FinFET device formed in a first region of the substrate and a tapered FinFET device in a second region of the substrate, the method includes, among other things, forming the fins for the non-tapered FinFET device in the first region by performing a fin-cut-last process and forming the fins for the tapered FinFET by performing a fin-cut-first process.

公开(公告)号：US20170213767A1

公开(公告)日：2017-07-27

申请号：US15006304

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/823481

Abstract: For an integrated circuit product comprising a non-tapered FinFET device formed in a first region of the substrate and a tapered FinFET device in a second region of the substrate, the method includes, among other things, forming the fins for the non-tapered FinFET device in the first region by performing a fin-cut-last process and forming the fins for the tapered FinFET by performing a fin-cut-first process.

公开(公告)号：US09595583B2

公开(公告)日：2017-03-14

申请号：US15060052

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min Gyu Sung

IPC: H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

公开(公告)号：US09543416B2

公开(公告)日：2017-01-10

申请号：US14536026

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L27/11

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/66553 ,  H01L29/6681

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.

Abstract translation: 本文公开的一种说明性方法包括在衬底的第一区域中形成第一多个鳍片，在衬底的第二区域中形成第二多个鳍片，以及在衬底中的两个相邻鳍片之间的空间 第二区域，其对应于将形成在第二区域中的第一隔离区域，在基板的第一和第二区域上方形成散热片去除掩模层，其中散热片移除掩模层具有位于至少一部分上方的开口 在第二区域中的所有第二多个散热片和第一隔离区域的空间中遮挡所有的第一多个散热片中的至少一个，并且通过第一开口执行蚀刻处理以去除至少一个 第一组多个翅片。