公开(公告)号：US20160379883A1

公开(公告)日：2016-12-29

申请号：US14749843

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Andrew J. Martin ,  Jennifer A. Oakley

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481

Abstract: A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.

Abstract translation: 一种在集成电路（IC）芯片和IC芯片上形成硅通孔（TSV）的方法。 在IC芯片表面上的一层布线层上的TSV图案标识TSV位置。 蚀刻IC芯片TSV图案在每个TSV图案位置处通过堆叠打开杯形通孔到硅衬底。 蚀刻的堆叠形成用于硅衬底的TSV硬掩模开口（HMO）。 蚀刻通过由HMO掩蔽的硅衬底的通孔穿过IC连接IC电路，例如连接到芯片底部的信号线。

公开(公告)号：US09401303B2

公开(公告)日：2016-07-26

申请号：US14449185

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Jonathan E. Faltermeier ,  Mukta G. Farooq ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76251 ,  H01L21/02304 ,  H01L21/02334 ,  H01L21/02345 ,  H01L21/31105 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/78 ,  H01L27/1203 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

Abstract translation: 本发明一般涉及半导体结构和制造方法，更具体地说，涉及在处理期间将半导体晶片临时粘接到处理器晶片。 半导体晶片可以通过在处理器晶片的表面上形成牺牲层而临时地结合到处理器晶片，在牺牲层的表面上形成第一电介质层，在半导体晶片的表面上形成第二电介质层， 并且直接接合第一介电层和第二介电层以形成接合层。 在处理半导体晶片之后，可以通过借助透射通过处理器晶片的红外辐射降低牺牲层，与粘合层一起从处理器晶片中去除。

公开(公告)号：US09257336B2

公开(公告)日：2016-02-09

申请号：US14522633

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/014

Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

公开(公告)号：US20190172789A1

公开(公告)日：2019-06-06

申请号：US16266196

申请日：2019-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K Stamper ,  Mukta G. Farooq ,  John A Fitzsimmons

IPC: H01L23/532 ,  H01L21/762 ,  H01L23/48 ,  H01L23/00

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US20190043769A1

公开(公告)日：2019-02-07

申请号：US15665974

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D.W. Melville ,  Mukta G. Farooq

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  G01R31/28

Abstract: A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad structure over a substrate, the first probe pad structure including a first probe pad in electrical communication with the substrate; a second probe pad structure over the substrate, the second probe pad structure including a second probe pad in electrical communication with the substrate, wherein the second probe pad structure is laterally separated from the first probe pad structure; and a non-metal region between the first probe pad structure and the second probe pad structure. The split probe pad structure may be formed in a kerf region of the semiconductor structure. The non-metal region may include a dielectric material.

公开(公告)号：US10049979B2

公开(公告)日：2018-08-14

申请号：US15292721

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Ian D. W. Melville

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.

公开(公告)号：US20180165402A1

公开(公告)日：2018-06-14

申请号：US15378122

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe

IPC: G06F17/50 ,  H01L21/768

CPC classification number: G06F17/5077 ,  H01L21/76898

Abstract: Various embodiments include approaches for designing through-silicon vias (TSVs) in integrated circuits (ICs). In some cases, a method includes: identifying types of through-silicon vias (TSVs) for placement within an integrated circuit (IC) design based upon an electrical requirement for the TSVs, wherein the IC design includes distinct types of TSVs; calculating etch and fill rates for the IC design with the distinct types of TSVs with common etching and filling processes; and providing fabrication instructions to form the distinct types of TSVs according to the calculated etch and fill rates in the common processes.

公开(公告)号：US09966310B1

公开(公告)日：2018-05-08

申请号：US15837279

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

公开(公告)号：US20170186693A1

公开(公告)日：2017-06-29

申请号：US14982097

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76852 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US09633925B1

公开(公告)日：2017-04-25

申请号：US15081403

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Katsuyuki Sakuma ,  Mukta G. Farooq ,  Jae-Woong Nah

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29

CPC classification number: H01L21/76864 ,  H01L21/563 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473

Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.