公开(公告)号：US20170018452A1

公开(公告)日：2017-01-19

申请号：US14797337

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括在集成电路基板上的两个鳍结构之间形成隔离沟槽，使用可流动的化学气相沉积工艺在隔离沟槽中形成可流动的膜，并对可流动薄膜进行退火以形成 隔离沟槽中的氧化硅介电层。 使用包括N 2和H 2 O 2的工艺气体在小于约200℃的温度下进行退火。

公开(公告)号：US09502232B2

公开(公告)日：2016-11-22

申请号：US14321866

申请日：2014-07-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Sandeep Gaan ,  Zhiguo Sun ,  Huang Liu ,  Adam Selsley

IPC: H01L21/02 ,  H01L21/321

CPC classification number: H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/321

Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Abstract translation: 提供了一种用于制造分层电路结构的方法，其包括例如：在衬底上沉积第一材料层，第一材料层具有氧化的上表面; 在所述第一材料层的氧化的上表面上提供第二材料层; 并且在第二材料层在第一材料层的氧化的上表面上提供第二材料层期间，抑制一个或多个元件从第一材料层的氧化的上表面扩散到第一材料层或第二材料层中。 抑制可以包括一个或多个修饰第一材料层的特征，在第一材料层的氧化的上表面上形成保护层，或改变在提供第二材料层中使用的至少一个工艺参数。

公开(公告)号：US09466701B2

公开(公告)日：2016-10-11

申请号：US14244261

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sandeep Gaan ,  Sipeng Gu

IPC: H01L21/31 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/785

Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.

Abstract translation: 本文提供了用于制备用于接触着陆的集成电路，用于制造集成电路的工艺，以及根据这些工艺制备的集成电路的工艺。 用于制备用于接触着陆的集成电路的示例性方法包括提供包括具有源区和漏区的晶体管的半导体结构，其中源极和漏极区中的至少一个具有覆盖有接触蚀刻停止层的成形接触结构和 预金属介电材料。 用一种或多种各向异性蚀刻去除预金属介电材料，包括对前金属介电材料选择性的至少一种各向异性蚀刻。 并且，用接触蚀刻停止层材料选择性的第三各向异性蚀刻去除覆盖成形接触结构的接触蚀刻停止层，以露出成形的接触结构。

公开(公告)号：US20150303273A1

公开(公告)日：2015-10-22

申请号：US14258488

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09673039B2

公开(公告)日：2017-06-06

申请号：US14666787

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir Ray ,  Yiqun Liu ,  Jin Ping Liu ,  Fabio D'Addamio ,  Sandeep Gaan

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/28 ,  C23C16/30 ,  G11C11/22 ,  H01L29/51

CPC classification number: H01L21/02181 ,  C23C16/308 ,  G11C11/22 ,  H01L21/02189 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 Å thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

公开(公告)号：US09520395B2

公开(公告)日：2016-12-13

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US20160079242A1

公开(公告)日：2016-03-17

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： GUILLAUME BOUCHE ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

公开(公告)号：US09076645B1

公开(公告)日：2015-07-07

申请号：US14272554

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir Ray ,  Sandeep Gaan ,  Jin Ping Liu ,  Zhiguo Sun

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02112 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02255 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76828 ,  H01L2221/1047

Abstract: Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.

Abstract translation: 提供了电路结构制造方法，其包括：在基底之上提供层间结构，所述层间结构包括分散在电介质材料内的致孔剂; 并且脉冲激光退火层间结构以形成经处理的层间结构，脉冲激光退火聚合层间结构的电介质材料以形成聚合物电介质材料，其包括设置在其中的孔。 脉冲激光退火有助于通过部分地维持经处理的层间结构的结构完整性来提高经处理的层间结构的弹性模量，尽管在聚合物电介质材料内设置孔，其例如有助于降低经处理的层间结构的介电常数 夹层结构。

公开(公告)号：US08940650B2

公开(公告)日：2015-01-27

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US20140256141A1

公开(公告)日：2014-09-11

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。