公开(公告)号：US10707119B1

公开(公告)日：2020-07-07

申请号：US16246847

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl ,  Vimal K. Kamineni

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

公开(公告)号：US09111907B2

公开(公告)日：2015-08-18

申请号：US14146399

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Robert Miller

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/417 ,  H01L21/285 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

Abstract translation: 半导体晶体管具有在源极区域和漏极区域之间的半导体衬底，源极区域，漏极区域和沟道区域的结构。 在通道区域的上方设置有具有钨的顶部导电部分的金属栅极。 提供了源极区域和漏极区域上的第一氮化硅保护层和栅极区域上的第二氮化硅保护层。 第一氮化硅保护层和第二氮化硅保护层被配置为允许第一氮化硅保护层的穿通，同时防止蚀刻通过第二氮化硅保护层。 通过避免完全蚀刻栅极开口来保护源极和漏极硅化物，除非所用的蚀刻不会对硅化物造成伤害，或者在完全蚀刻用于栅极接触的栅极的开口之前产生硅化物和源极和漏极接触。

公开(公告)号：US20150129934A1

公开(公告)日：2015-05-14

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US20150041906A1

公开(公告)日：2015-02-12

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, JR.

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

公开(公告)号：US20200227308A1

公开(公告)日：2020-07-16

申请号：US16246847

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl ,  Vimal K. Kamineni

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

公开(公告)号：US10707132B2

公开(公告)日：2020-07-07

申请号：US16557195

申请日：2019-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US20190385912A1

公开(公告)日：2019-12-19

申请号：US16557128

申请日：2019-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US10014180B1

公开(公告)日：2018-07-03

申请号：US15681654

申请日：2017-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Neal A. Makela ,  Vimal K. Kamineni ,  Pei Liu ,  Chih-Chiang Chang

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L21/28568 ,  H01L21/0217 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/31055 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66568 ,  H01L2029/42388

Abstract: A structure and method for forming a tungsten region for a replacement metal gate (RMG). The method for forming the tungsten region may include, among other things, forming a first tungsten region i.e., tungsten seed layer, on a liner in a trench of a dielectric layer; removing a portion of the liner and the tungsten seed layer to expose an uppermost surface of a work function metal (WFM) layer wherein an uppermost surface of the liner and tungsten seed layer is positioned below an uppermost surface of the dielectric layer; and forming a second tungsten region from the tungsten seed layer. The tungsten region may be formed to contact the uppermost surface liner, the uppermost surface of WFM layer, and/or the sidewalls of the trench. The tungsten region may include a single crystallographic orientation. The tungsten region may also include an uppermost surface with a substantially arcuate cross-sectional geometry.

公开(公告)号：US09093302B2

公开(公告)日：2015-07-28

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US20150187945A1

公开(公告)日：2015-07-02

申请号：US14146430

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Robert Miller

IPC: H01L29/78 ,  H01L29/45 ,  H01L21/283 ,  H01L29/417 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A gate is provided above the channel region. A silicon nitride protective layer is provided over the source region and the drain region, along with a silicon nitride cap over the gate region. The silicon nitride protective layer is configured to allow punch-through of the protective layer after source and drain openings are created, while preventing etching through the cap above the gate. The self-aligned source, drain and gate contacts are formed while protecting the source and drain salicide using the silicon nitride protective layer and gate cap.

Abstract translation: 半导体晶体管具有在源极区域和漏极区域之间的半导体衬底，源极区域，漏极区域和沟道区域的结构。 在通道区域上方设置一个门。 氮化硅保护层与栅极区域上的氮化硅盖一起设置在源极区域和漏极区域上。 氮化硅保护层被配置为允许在产生源极和漏极开口之后穿透保护层，同时防止蚀刻通过栅极上方的帽。 在使用氮化硅保护层和栅极盖保护源极和漏极自对准硅化物的同时形成自对准的源极，漏极和栅极接触。