公开(公告)号：US09330982B1

公开(公告)日：2016-05-03

申请号：US14826276

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Jinping Liu ,  In Soo Jung

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/2255 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of forming a diffusion barrier film over fins and the resulting device are provided. Embodiments include forming silicon fins over a substrate; depositing a borosilicate glass (BSG) liner cap over a first set of the silicon fins; depositing a phosphosilicate (PSG) liner cap over a second set of the silicon fins; and depositing a silicon oxycarbide (SiOC) diffusion barrier film over the BSG and PSG liner caps.

Abstract translation: 提供了一种在翅片上形成扩散阻挡膜的方法和所得到的器件。 实施例包括在衬底上形成硅散热片; 在第一组硅片上沉积硼硅酸盐玻璃（BSG）衬垫帽; 在第二组硅片上沉积磷硅酸盐（PSG）衬垫帽; 并在BSG和PSG衬套上沉积硅碳氧化物（SiOC）扩散阻挡膜。

公开(公告)号：US10453751B2

公开(公告)日：2019-10-22

申请号：US15432016

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng Qiu ,  Michael V. Aquilino ,  Patrick D. Carpenter ,  Jessica Dechene ,  Ming Hao Tang ,  Haigou Huang ,  Huy Cao

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/768 ,  H01L29/423 ,  H01L27/088 ,  H01L21/033 ,  H01L21/311 ,  H01L29/417

Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

公开(公告)号：US10043753B2

公开(公告)日：2018-08-07

申请号：US15377592

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy Cao ,  Zhiguo Sun ,  Joseph F. Shepard, Jr. ,  Moosung M. Chae

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

公开(公告)号：US09318440B2

公开(公告)日：2016-04-19

申请号：US14799116

申请日：2015-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Huang Liu ,  Garo Jacques Derderian ,  Boaz Alperson

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract translation: 提供电路结构的导电接触结构及其制造方法。 该制造包括例如提供设置在半导体衬底上的至少一个接触开口; 在所述半导体衬底上设置的所述至少一个接触开口中形成具有固定碳含量的富碳接触衬垫材料。

公开(公告)号：US10460986B2

公开(公告)日：2019-10-29

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10256089B2

公开(公告)日：2019-04-09

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20180366324A1

公开(公告)日：2018-12-20

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L21/02378 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/28255 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76888 ,  H01L29/41775

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US09991363B1

公开(公告)日：2018-06-05

申请号：US15657594

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinsheng Gao ,  Haifeng Sheng ,  Jinping Liu ,  Huy Cao ,  Hui Zang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32105 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437

Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

公开(公告)号：US09793169B1

公开(公告)日：2017-10-17

申请号：US15175187

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Huang Liu ,  Guillaume Bouche ,  Songkram Srivathanakul

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3115 ,  H01L29/66795

Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.