公开(公告)号：US09640636B1

公开(公告)日：2017-05-02

申请号：US15171795

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven J. Bentley ,  John H. Zhang ,  Kwan-Yong Lim ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.

公开(公告)号：US09530866B1

公开(公告)日：2016-12-27

申请号：US15097621

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/66666 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/7827

Abstract: Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.

Abstract translation: 形成与垂直取向的沟道半导体结构（“VCS结构”）相邻并且与覆盖层相邻的第一侧壁间隔物，执行至少一个平坦化处理，以平坦化绝缘材料并暴露盖层的上表面和上表面 并且去除所述第一间隔物的一部分和所述盖层的整体，从而暴露所述VCS结构的上表面并且在所述VCS结构和所述第一间隔物之上限定间隔物/接触腔。 该方法还包括在间隔物/接触腔中形成第二间隔物，在VCS结构中形成顶部源极/漏极区域，并在间隔物/接触腔内形成顶部源极/漏极接触，导电耦合到顶部源极/漏极 区域，其中所述导电接触物质地接触所述间隔件/接触腔中的所述第二间隔件。

公开(公告)号：US10651293B2

公开(公告)日：2020-05-12

申请号：US15840835

申请日：2017-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165

Abstract: A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.

公开(公告)号：US10461186B1

公开(公告)日：2019-10-29

申请号：US15994392

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Ruilong Xie ,  Mahender Kumar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

Abstract: Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US10157832B2

公开(公告)日：2018-12-18

申请号：US15453133

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a first metal level including a first metal line within a first dielectric layer; a second metal level including a second metal line in a second dielectric layer, the second metal level being over the first metal level; a first via interconnect structure extending through the first metal level and through the second metal level, wherein the first via interconnect structure abuts a first lateral of the first metal line and a first lateral end of the second metal line, and wherein the first via interconnect structure is a vertically uniform structure and includes a first metal.

公开(公告)号：US20180323067A1

公开(公告)日：2018-11-08

申请号：US15587597

申请日：2017-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xusheng Yu ,  John H. Zhang ,  Xiaoqiang Zhang

IPC: H01L21/033 ,  H01L23/525 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31116 ,  H01L21/768 ,  H01L23/5256 ,  H01L23/53214 ,  H01L23/53228

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first mandrel line, a second mandrel line, and a non-mandrel line between the first mandrel line and the second mandrel line are provided. A first sidewall spacer is formed adjacent to a section of the first mandrel line and is arranged between the section of the first mandrel line and the non-mandrel line. A first cut is formed that extends partially across the non-mandrel line adjacent to the first spacer to narrow a section of the non-mandrel line. The section of the first mandrel line is removed selective to the first sidewall spacer to form a second cut. An interconnect is formed using the non-mandrel line. The interconnect includes a narrowed section coinciding with a location of the narrowed section of the non-mandrel line.

公开(公告)号：US20180261536A1

公开(公告)日：2018-09-13

申请号：US15453133

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a first metal level including a first metal line within a first dielectric layer; a second metal level including a second metal line in a second dielectric layer, the second metal level being over the first metal level; a first via interconnect structure extending through the first metal level and through the second metal level, wherein the first via interconnect structure abuts a first lateral of the first metal line and a first lateral end of the second metal line, and wherein the first via interconnect structure is a vertically uniform structure and includes a first metal.

公开(公告)号：US09837553B1

公开(公告)日：2017-12-05

申请号：US15282415

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  John H. Zhang ,  Haigou Huang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (VFETs) and methods of manufacture. The VFET includes: one or more vertical fin structures; a source region positioned at a first location on a top surface of the one or more vertical fin structures; a drain region positioned at a second location on the top surface of the one or more vertical fin structures at a predetermined distance away from the source region, along a length thereof; and a gate channel along the predetermined distance and in electrical contact with the source region and the drain region.

公开(公告)号：US20170301776A1

公开(公告)日：2017-10-19

申请号：US15132383

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Steven J. Bentley ,  Kwan-Yong Lim

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.