公开(公告)号：US20130178033A1

公开(公告)日：2013-07-11

申请号：US13786372

申请日：2013-03-05

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US08193641B2

公开(公告)日：2012-06-05

申请号：US11431388

申请日：2006-05-09

申请人： Willy Rachmady ,  Brian McIntyre ,  Michael K. Harper ,  Subhash M. Joshi

发明人： Willy Rachmady ,  Brian McIntyre ,  Michael K. Harper ,  Subhash M. Joshi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66553

摘要： A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

摘要翻译： 晶体管栅极包括具有设置在表面上的一对间隔物的衬底，在隔离体之间保形地沉积在衬底上的高k电介质，共形沉积在高k电介质上并沿着间隔壁侧壁的一部分的凹陷功函数金属 保形地沉积在凹陷功函数金属上的第二功函件金属和沉积在第二功函数金属上的电极金属。 晶体管栅极可以通过将高k电介质保形地沉积到衬底上的间隔物之间​​的沟槽中而形成，从而在高k电介质顶部上共形沉积功函数金属，在功函数金属顶部沉积牺牲掩模，蚀刻部分 牺牲掩模以暴露所述功函数金属的一部分，以及蚀刻所述功函数金属的暴露部分以形成所述凹陷功函数金属。 第二功函数金属和电极金属可沉积在凹陷功函数金属顶上。

公开(公告)号：US20170040218A1

公开(公告)日：2017-02-09

申请号：US15299106

申请日：2016-10-20

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/51

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US09419106B2

公开(公告)日：2016-08-16

申请号：US13993332

申请日：2011-09-30

申请人： Subhash M. Joshi ,  Michael Hattendorf

发明人： Subhash M. Joshi ,  Michael Hattendorf

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.

摘要翻译： 本发明涉及非平面晶体管内的形成源极/漏极结构，其中从非平面晶体管去除翅片间隔物，以便从非平面晶体管鳍片形成源/漏结构， 具有适当材料的平面晶体管鳍片以形成源极/漏极结构。

公开(公告)号：US08981435B2

公开(公告)日：2015-03-17

申请号：US13992550

申请日：2011-10-01

申请人： Sameer S. Pradhan ,  Subhash M. Joshi ,  Jin-Sung Chun

发明人： Sameer S. Pradhan ,  Subhash M. Joshi ,  Jin-Sung Chun

IPC分类号： H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L23/48 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/785 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/48 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

摘要翻译： 本说明书涉及制造具有非平面晶体管的微电子器件的领域。 本发明的实施例涉及在非平面晶体管内形成源极/漏极接触，其中可以使用含钛接触界面来形成源极/漏极接触，其中形成在含钛的 界面和含硅源/排水结构。

公开(公告)号：US07250678B2

公开(公告)日：2007-07-31

申请号：US10776448

申请日：2004-02-10

申请人： Madhav Datta ,  Dave Emory ,  Subhash M. Joshi ,  Susanne Menezes ,  Doowon Suh

发明人： Madhav Datta ,  Dave Emory ,  Subhash M. Joshi ,  Susanne Menezes ,  Doowon Suh

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

公开(公告)号：US20140151817A1

公开(公告)日：2014-06-05

申请号：US14174822

申请日：2014-02-06

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L29/51

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US20130264617A1

公开(公告)日：2013-10-10

申请号：US13993332

申请日：2011-09-30

申请人： Subhash M. Joshi ,  Michael Hattendorf

发明人： Subhash M. Joshi ,  Michael Hattendorf

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.

摘要翻译： 本发明涉及非平面晶体管内的形成源极/漏极结构，其中从非平面晶体管去除翅片间隔物，以便从非平面晶体管鳍片形成源/漏结构， 具有适当材料的平面晶体管鳍片以形成源极/漏极结构。

公开(公告)号：US08436404B2

公开(公告)日：2013-05-07

申请号：US12655408

申请日：2009-12-30

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20120264285A1

公开(公告)日：2012-10-18

申请号：US13479078

申请日：2012-05-23

申请人： Willy Rachmady ,  Brian Mclntyre ,  Michael K. Harper ,  Subhash M. Joshi

发明人： Willy Rachmady ,  Brian Mclntyre ,  Michael K. Harper ,  Subhash M. Joshi

IPC分类号： H01L21/283

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66553

摘要： A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

摘要翻译： 晶体管栅极包括具有设置在表面上的一对间隔物的衬底，在隔离体之间保形地沉积在衬底上的高k电介质，共形沉积在高k电介质上并沿着间隔壁侧壁的一部分的凹陷功函数金属 保形地沉积在凹陷功函数金属上的第二功函件金属和沉积在第二功函数金属上的电极金属。 晶体管栅极可以通过将高k电介质保形地沉积到衬底上的间隔物之间​​的沟槽中而形成，从而在高k电介质顶部上共形沉积功函数金属，在功函数金属顶部沉积牺牲掩模，蚀刻部分 牺牲掩模以暴露所述功函数金属的一部分，以及蚀刻所述功函数金属的暴露部分以形成所述凹陷功函数金属。 第二功函数金属和电极金属可沉积在凹陷功函数金属顶上。