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    SELF-ALIGNED CONTACTS FOR NANOSHEET FIELD EFFECT TRANSISTOR DEVICES
    11.
    发明申请
    SELF-ALIGNED CONTACTS FOR NANOSHEET FIELD EFFECT TRANSISTOR DEVICES 有权

    公开(公告)号：US20210183711A1

    公开(公告)日：2021-06-17

    申请号：US17110604

    申请日：2020-12-03

    Applicant: IMEC vzw

    Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

    Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

    Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure
    13.
    发明申请
    Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure 有权
    形成包括鳍形通道结构的晶体管结构的方法

    公开(公告)号：US20160126131A1

    公开(公告)日：2016-05-05

    申请号：US14924832

    申请日：2015-10-28

    Applicant: IMEC VZW

    Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

    IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

    CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

    Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

    FinFET having locally higher fin-to-fin pitch
    14.
    发明授权
    FinFET having locally higher fin-to-fin pitch 有权

    公开(公告)号：US11114435B2

    公开(公告)日：2021-09-07

    申请号：US15382376

    申请日：2016-12-16

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Geert Hellings ,  Roman Boschke ,  Dimitri Linten ,  Naoto Horiguchi

    IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

    Internal spacers for nanowire semiconductor devices
    15.
    发明授权
    Internal spacers for nanowire semiconductor devices 有权

    公开(公告)号：US10361268B2

    公开(公告)日：2019-07-23

    申请号：US15907878

    申请日：2018-02-28

    Applicant: IMEC VZW

    Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

    IPC: H01L29/06 ,  H01L29/66 ,  B82Y40/00 ,  H01L21/8234 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L21/311

    Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

    Method for manufacturing a field effect transistor of a non-planar type
    18.
    发明授权
    Method for manufacturing a field effect transistor of a non-planar type 有权
    制造非平面型场效应晶体管的方法

    公开(公告)号：US09105746B2

    公开(公告)日：2015-08-11

    申请号：US14521083

    申请日：2014-10-22

    Applicant: IMEC VZW

    Inventor： Min-Soo Kim ,  Guillaume Boccardi ,  Soon Aik Chew ,  Naoto Horiguchi

    IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10

    CPC classification number: H01L21/823821 ,  H01L21/02126 ,  H01L21/76205 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

    Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

    Abstract translation: 一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构 衬底之间的浅沟槽隔离结构。 浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。 该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由 电介质间隔结构。 此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

    SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
    20.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210028068A1

    公开(公告)日：2021-01-28

    申请号：US16938168

    申请日：2020-07-24

    Applicant: IMEC vzw

    Inventor： Eugenio Dentoni Litta ,  Yusuke Oniki ,  Lars-Ake Ragnarsson ,  Naoto Horiguchi

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423

    Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.

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