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    Chip package structure
    18.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11239168B2

    公开(公告)日：2022-02-01

    申请号：US16849999

    申请日：2020-04-16

    Applicant: Industrial Technology Research Institute

    Inventor： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

    IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L25/065

    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE
    19.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210082810A1

    公开(公告)日：2021-03-18

    申请号：US17095744

    申请日：2020-11-12

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

    IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

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