公开(公告)号：US20170373138A1

公开(公告)日：2017-12-28

申请号：US15458492

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/768 ,  H01L29/78 ,  H03F1/02 ,  H03F3/193

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7823 ,  H03F1/0288 ,  H03F3/193 ,  H03F2200/451

Abstract: In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US20170069554A1

公开(公告)日：2017-03-09

申请号：US15352392

申请日：2016-11-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/66 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract translation: 一种形成电子器件的方法包括在工件中形成第一开口和第二开口。 第一个开口比第二个开口更深。 该方法还包括在第一开口内形成填充材料以形成通孔的一部分，并在第二开口内形成填充材料。

公开(公告)号：US20150364402A1

公开(公告)日：2015-12-17

申请号：US14834846

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L23/48 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract translation: 根据本发明的实施例，一种形成电子装置的方法包括在工件中形成第一开口和第二开口。 第一个开口比第二个开口更深。 该方法还包括在第一开口内形成填充材料以形成通孔的一部分，并在第二开口内形成填充材料。

公开(公告)号：US20150035171A1

公开(公告)日：2015-02-05

申请号：US13958276

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

Abstract translation: 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US11929405B2

公开(公告)日：2024-03-12

申请号：US17228973

申请日：2021-04-13

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US11869963B2

公开(公告)日：2024-01-09

申请号：US17733009

申请日：2022-04-29

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/26546 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66462

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US11302783B2

公开(公告)日：2022-04-12

申请号：US16694070

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/45 ,  H01L29/20 ,  H01L21/283 ,  H01L29/40 ,  H01L29/778

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

公开(公告)号：US20210336043A1

公开(公告)日：2021-10-28

申请号：US17237178

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US10340334B2

公开(公告)日：2019-07-02

申请号：US15986942

申请日：2018-05-23

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H03F1/02 ,  H03F3/193 ,  H01L23/48

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

公开(公告)号：US20180350981A1

公开(公告)日：2018-12-06

申请号：US16100676

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L29/10 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L29/7816 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/1095 ,  H01L29/66681

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.