公开(公告)号：US20210246016A1

公开(公告)日：2021-08-12

申请号：US17150527

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Stephan Pindl ,  Carsten Ahrens ,  Stefan Jost ,  Ulrich Krumbein ,  Matthias Reinwald

IPC: B81B7/00 ,  B81C1/00 ,  G01N29/24 ,  G01N33/00

Abstract: An infrared emitter with a glass lid for emitting infrared radiation comprises a package enclosing a cavity, wherein a first part is transparent for infrared radiation and a second part comprises a glass material and a heating structure configured for emitting the infrared radiation, wherein the heating structure is arranged in the cavity between the first part and the second part of the package.

公开(公告)号：US20210057528A1

公开(公告)日：2021-02-25

申请号：US16997980

申请日：2020-08-20

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Carsten Ahrens ,  Matthias Zigldrum

IPC: H01L29/20 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes a composite layer having a first and second opposing surfaces. The composite layer includes a mesa and a first insulating layer. The mesa has top and bottom surfaces and side faces. The side faces are embedded in the first insulating layer. The mesa includes a Group III nitride-based multilayer structure providing a Group III nitride based device having first and second electrodes arranged on the mesa top surface. First and second outer contacts are positioned on the second surface of the composite layer. A first conductive via extends through the first insulating layer and is electrically coupled to the first electrode on the mesa top surface and to the first outer contact. A second conductive via extends through the first insulating layer and is electrically coupled to the second electrode on the mesa top surface and to the second outer contact.

公开(公告)号：US10384934B2

公开(公告)日：2019-08-20

申请号：US15923599

申请日：2018-03-16

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Stephan Pindl ,  Bernhard Knott ,  Carsten Ahrens

IPC: B81C1/00 ,  H04R19/00 ,  H04R19/04 ,  H04R31/00

Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack over a first main surface of a substrate, forming a polymer layer over a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

公开(公告)号：US09524940B2

公开(公告)日：2016-12-20

申请号：US15003820

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L21/784 ,  H01L21/288 ,  H01L21/78 ,  H01L23/495 ,  H01L23/482

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

公开(公告)号：US09458009B2

公开(公告)日：2016-10-04

申请号：US14798112

申请日：2015-07-13

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Carsten Ahrens ,  Stefan Barzen ,  Wolfgang Friza

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/0072 ,  B81B3/001 ,  B81B3/0027 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00182 ,  B81C1/00404 ,  B81C1/00984 ,  B81C2201/017 ,  B81C2201/115

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface. A membrane is formed over the sacrificial layer. A through hole is etched through the workpiece from the second surface to expose a surface of the sacrificial layer. At least a portion of the sacrificial layer is removed from the second surface to form a cavity under the membrane. The cavity is aligned with the membrane.

公开(公告)号：US20160141256A1

公开(公告)日：2016-05-19

申请号：US15003820

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/00 ,  H01L21/288 ,  H01L23/495 ,  H01L21/78

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

公开(公告)号：US20150137305A1

公开(公告)日：2015-05-21

申请号：US14566751

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

IPC: H01L27/02 ,  H01L29/868 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

Abstract: Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode.

Abstract translation: 这里描述的是保护结构。 保护结构包括半导体衬底，设置在半导体衬底中或半导体衬底中的至少一个上的第一二极管和设置在半导体衬底中或半导体衬底中的至少之一上的二极管布置。 二极管装置包括与第二二极管串联连接的第二二极管和瞬态电压抑制器（TVS）二极管的堆叠。 二极管布置与第一二极管并联。

公开(公告)号：US20150069591A1

公开(公告)日：2015-03-12

申请号：US14023493

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract translation: 根据各种实施例，半导体器件的制造方法可以包括提供半导体工件，其包括在半导体工件的第一侧的器件区域，其中半导体工件的机械稳定性不足以抵抗至少一个后端工艺，而没有 损坏，并且在半导体工件的与半导体工件的第一侧相对的第二侧上沉积至少一个导电层，其中至少一个导电层增加半导体工件的机械稳定性，以足以抵抗至少一个 后端程序无损坏。

公开(公告)号：US20140097514A1

公开(公告)日：2014-04-10

申请号：US13647740

申请日：2012-10-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Klaus Elian ,  Jens Pohl ,  Horst Theuss ,  Renate Hofmann ,  Alexander Glas ,  Carsten Ahrens

IPC: H01L27/08 ,  H01L21/78

CPC classification number: H01L23/295 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5227 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2224/03 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.

Abstract translation: 半导体封装包括半导体芯片，施加到半导体芯片的电感器。 电感器包括至少一个绕组。 至少一个绕组内的空间填充有磁性材料。

公开(公告)号：US20130239404A1

公开(公告)日：2013-09-19

申请号：US13888185

申请日：2013-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Carsten Ahrens ,  Gunther Mackh ,  Klemens Pruegl

IPC: H01F41/04 ,  H05K3/10

CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F17/0006 ,  H01F17/04 ,  H01F27/255 ,  H01F41/046 ,  H01F2017/048 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/30107 ,  H05K3/10 ,  Y10T29/49075 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01005

Abstract: In one embodiment, an inductor has a substrate, a conductor disposed above the substrate and a seamless ferromagnetic material surrounding at least a first portion of the conductor.

Abstract translation: 在一个实施例中，电感器具有衬底，布置在衬底上方的导体和围绕导体的至少第一部分的无缝铁磁材料。