公开(公告)号：US11211324B2

公开(公告)日：2021-12-28

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US12293913B1

公开(公告)日：2025-05-06

申请号：US17559363

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Richard E. Schenker ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Gauri Nabar ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/027

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.

公开(公告)号：US20240204083A1

公开(公告)日：2024-06-20

申请号：US18066307

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  Florian Gstrein ,  Charles Henry Wallace ,  Eungnak Han ,  Leonard P. Guler

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L29/6656 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L29/66545 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2924/15311

Abstract: DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.

公开(公告)号：US20240202415A1

公开(公告)日：2024-06-20

申请号：US18068601

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Quan Shi ,  Patrick Morrow ,  Charles Henry Wallace ,  Lars Liebmann ,  Thi Nguyen ,  Sivakumar Venkataraman ,  Nikolay Ryzhenko Vladimirovich ,  Xinning Wang ,  Douglas Stout

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.

公开(公告)号：US12002678B2

公开(公告)日：2024-06-04

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20220190129A1

公开(公告)日：2022-06-16

申请号：US17123828

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Changyok Park ,  Guillaume Bouche ,  Hyuk Ju Ryu ,  Charles Henry Wallace ,  Mohit K. Haran

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/10

Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

公开(公告)号：US20250029915A1

公开(公告)日：2025-01-23

申请号：US18884558

申请日：2024-09-13

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Charles Henry Wallace ,  Paul A. Nyhus

IPC: H01L23/522 ,  G06F1/16 ,  H01L21/768 ,  H01L23/14 ,  H01L23/50 ,  H01L23/528

Abstract: Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.

公开(公告)号：US12131989B2

公开(公告)日：2024-10-29

申请号：US17099823

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Charles Henry Wallace ,  Paul A. Nyhus

IPC: H01L21/768 ,  G06F1/16 ,  H01L23/14 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5222 ,  G06F1/16 ,  H01L21/76838 ,  H01L23/142 ,  H01L23/50 ,  H01L23/528

Abstract: Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.

公开(公告)号：US12087594B2

公开(公告)日：2024-09-10

申请号：US17124730

申请日：2020-12-17

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Eungnak Han ,  Manish Chandhok ,  Richard E Schenker ,  Florian Gstrein ,  Paul A. Nyhus ,  Charles Henry Wallace

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831

Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：US20240249946A1

公开(公告)日：2024-07-25

申请号：US18625348

申请日：2024-04-03

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.