公开(公告)号：US10070537B2

公开(公告)日：2018-09-04

申请号：US15065620

申请日：2016-03-09

Applicant: INTEL CORPORATION

Inventor： Deepak Arora ,  Daniel N. Sobieski ,  Dilan Seneviratne ,  Ebrahim Andideh ,  James C. Meyer

IPC: B32B38/10 ,  H05K3/46 ,  C23C14/22 ,  H05K3/42 ,  H05K3/10 ,  H01L21/48 ,  B32B43/00 ,  H01L21/44 ,  H05K3/00 ,  H05K3/28 ,  H01L21/56

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

公开(公告)号：US09899311B2

公开(公告)日：2018-02-20

申请号：US15370432

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Daniel N. Sobieski ,  Mihir K. Roy ,  William J. Lambert

IPC: H01L23/52 ,  H01L23/498 ,  H01L21/02 ,  H01L21/285 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/00 ,  H01L21/48 ,  H05K1/16

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20170362684A1

公开(公告)日：2017-12-21

申请号：US15674184

申请日：2017-08-10

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Amruthavalli P. Alur ,  Daniel N. Sobieski

IPC: C22C9/00 ,  H01L23/498 ,  H01L23/12 ,  H01L23/49

CPC classification number: C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

公开(公告)号：US09758845B2

公开(公告)日：2017-09-12

申请号：US14773108

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Amruthavalli P. Alur ,  Daniel N. Sobieski

IPC: H05K1/09 ,  C22C9/00 ,  H01L23/12 ,  H01L23/49 ,  H01L23/498

CPC classification number: C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

公开(公告)号：US20170092575A1

公开(公告)日：2017-03-30

申请号：US15370432

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Daniel N. Sobieski ,  Mihir K. Roy ,  William J. Lambert

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/16 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20160192508A1

公开(公告)日：2016-06-30

申请号：US15065620

申请日：2016-03-09

Applicant: INTEL CORPORATION

Inventor： Deepak Arora ,  Daniel N. Sobieski ,  Dilan Seneviratne ,  Ebrahim Andideh ,  James C. Meyer

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/42 ,  C23C14/22 ,  C23C14/34

CPC classification number: H05K3/4644 ,  B32B38/10 ,  B32B43/006 ,  C23C14/228 ,  H01L21/44 ,  H01L21/48 ,  H01L21/565 ,  H05K3/0014 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/107 ,  H05K3/281 ,  H05K3/42 ,  H05K2203/0554 ,  H05K2203/1105 ,  H05K2203/1152 ,  Y10T156/1168 ,  Y10T156/1978

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于形成具有光滑表面的电介质的技术和配置。 在一个实施例中，一种方法包括提供具有第一表面和第二表面的电介质，形成在第一表面上的导电特征，以及施加到第二表面的层压板，在层压体保持施加时固化第二表面，以及去除层压体。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160086894A1

公开(公告)日：2016-03-24

申请号：US14491892

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： DIGVIJAY A. RORANE ,  Ian En Yoon Chin ,  Daniel N. Sobieski

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/50 ,  H01L23/3121 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Abstract translation: 实施例包括半导体器件封装和形成这种封装的方法。 在一个实施例中，包装可以包括具有通过模头侧加强层形成的腔的模头侧加强层。 具有第一侧和包括器件侧的相对的第二侧的管芯可以定位在腔中，其中管芯的第一侧与模具侧加强层的第一侧基本上共面。 在一个实施例中，积聚结构可以联接到管芯的第二侧。 实施例包括包含图案化导电材料和绝缘材料的多个交替层的堆积结构。