公开(公告)号：US09379010B2

公开(公告)日：2016-06-28

申请号：US14163323

申请日：2014-01-24

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract translation: 用于在电介质层内形成具有窄间距互连结构的互连层的工艺，其中用于形成互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的潜力。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：US12150297B2

公开(公告)日：2024-11-19

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Arnab Sen Gupta ,  Matthew V. Metz ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang

IPC: H10B12/00 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：US11854787B2

公开(公告)日：2023-12-26

申请号：US17735006

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53238 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US10811351B2

公开(公告)日：2020-10-20

申请号：US16316528

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Elliot N. Tan

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/498

Abstract: A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.

公开(公告)号：US09659860B2

公开(公告)日：2017-05-23

申请号：US14905269

申请日：2013-08-21

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Elliot N. Tan

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.

公开(公告)号：US11950407B2

公开(公告)日：2024-04-02

申请号：US16828507

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Juan G. Alzate Vinasco ,  Travis W. Lajoie ,  Abhishek A. Sharma ,  Kimberly L Pierce ,  Elliot N. Tan ,  Yu-Jin Chen ,  Van H. Le ,  Pei-Hua Wang ,  Bernhard Sell

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/91 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/318 ,  H10B12/482 ,  H10B12/485

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20230290825A1

公开(公告)日：2023-09-14

申请号：US17693136

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Sean Pursel ,  Raghuram Gandikota ,  Sikandar Abbas ,  Tsuan-Chung Chang ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Elliot N. Tan

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/66742 ,  H01L27/0886

Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

公开(公告)号：US10211088B2

公开(公告)日：2019-02-19

申请号：US15743616

申请日：2015-09-10

Applicant: INTEL CORPORATION ,  Charles H. Wallace ,  Swaminathan Sivakumar

Inventor： Charles H. Wallace ,  Elliot N. Tan ,  Paul A. Nyhus ,  Swaminathan Sivakumar

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033

Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

公开(公告)号：US10204830B2

公开(公告)日：2019-02-12

申请号：US15730647

申请日：2017-10-11

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Paul A. Nyhus ,  Elliot N. Tan ,  Swaminathan Sivakumar

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.

公开(公告)号：US09793159B2

公开(公告)日：2017-10-17

申请号：US14911991

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Paul A. Nyhus ,  Elliot N. Tan ,  Swaminathan Sivakumar

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.