公开(公告)号：US11754861B2

公开(公告)日：2023-09-12

申请号：US17360160

申请日：2021-06-28

Applicant: INTEL CORPORATION

Inventor： Taehwan Kim ,  Ganesh Balamurugan ,  Hao Li ,  Hasitha Jayatilleka

IPC: G02F1/01

CPC classification number: G02F1/0136

Abstract: Embodiments include apparatuses, methods, and systems including a dynamic polarization controller (DPC) to receive a first light beam and a second light beam, to adjust a rotation of a state of polarization (SOP) of the first light beam and the second light beam to generate a third light beam and a fourth light beam, under the control of a first control signal, a second control signal, and a third control signal. The first control signal may be related to a phase difference between the third light beam and the fourth light beam, the second control signal may be related to an intensity difference between the third light beam and the fourth light beam, and the third control signal may be related to a rotation of a SOP of the third light beam and the fourth light beam. Other embodiments may also be described and claimed.

公开(公告)号：US11722128B2

公开(公告)日：2023-08-08

申请号：US17357456

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

CPC classification number: H03K5/1565 ,  G06F1/08 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US10924305B2

公开(公告)日：2021-02-16

申请号：US16305116

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Aruna Kumar ,  Anoop Karunan ,  Ganesh Balamurugan ,  Prakash Radhakrishnan

IPC: H04L25/02 ,  H04L25/03 ,  H04L1/24 ,  H04L7/10 ,  H04L25/08 ,  H04N21/4363

Abstract: Disclosed herein are devices and methods to facilitate compensating for intra-pair skew in a high-definition multimedia interface (HDMI) system. One or more skew training pattern may be transmitted on a signal line including a differential pair. Acknowledgment of receiving the skew training pattern may be received on a display data channel (DDC) associated with HDMI system. The skew training pattern may be used to ascertain and compensate for intra-pair skew.

公开(公告)号：US10664430B2

公开(公告)日：2020-05-26

申请号：US16258429

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Tzu-Chien Hsueh ,  Ganesh Balamurugan ,  Bryan K. Casper

IPC: G06F13/40 ,  G06F1/18 ,  H04L25/02 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/36 ,  G06F13/20 ,  G06F13/42

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

公开(公告)号：US10606004B2

公开(公告)日：2020-03-31

申请号：US15995694

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Jahnavi Sharma ,  Ganesh Balamurugan ,  Hao Li ,  Meer Nazmus Sakib ,  Haisheng Rong

IPC: G02B6/43 ,  H01L27/146 ,  H04B10/67 ,  G02B6/12 ,  H01L31/12 ,  H01L31/14 ,  H04B10/66

Abstract: Embodiments herein may relate to an optoelectronic receiver that includes a photonic integrated circuit (PIC) coupled with a light source. Respective PIC sections of the PIC may include a photodiode and a junction capacitor. The optoelectronic receiver may further include an electronic integrated circuit (EIC) coupled with the PIC. Respective EIC sections of the EIC may be communicatively coupled to respective ones of the PIC sections. Other embodiments may be described and/or claimed.

公开(公告)号：US20160379695A1

公开(公告)日：2016-12-29

申请号：US14750670

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Ashoke Ravi ,  Dinesh Somasekhar ,  Ganesh Balamurugan ,  Sudip Shekhar ,  Tawfiq Musah ,  Tzu-Chien Hsueh

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/161 ,  G05F3/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H03H11/22 ,  H03K3/356104 ,  H03K19/018557 ,  H03K19/018585 ,  H03M1/12 ,  H03M1/362 ,  H03M1/66 ,  H03M1/765 ,  H04L25/00

Abstract: Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (Mils). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

Abstract translation: 实施例包括耦合在信号路径上的电阻器，其包括一个或多个电阻性存储器元件，诸如一个或多个磁性隧道结（Mils）。 电阻式存储器元件的电阻可以被数字可修整以调节电阻器在信号路径上的电阻。 电阻器可以并入到模拟或混合信号电路中，以在信号路径上传递模拟信号。 可以描述和要求保护其他实施例。

公开(公告)号：US20240204879A1

公开(公告)日：2024-06-20

申请号：US18523592

申请日：2023-11-29

Applicant: Intel Corporation

Inventor： Duanni Huang ,  Xinru Wu ,  Taehwan Kim ,  Ganesh Balamurugan ,  Haisheng Rong

IPC: H04B10/50 ,  H04B10/69

CPC classification number: H04B10/503 ,  H04B10/6911

Abstract: Embodiments herein relate to an optical system coupled with or including a control logic. The control logic may be configured to identify, based on feedback provided by a photodiode (PD) of an optical receiver, that an amplitude of an optical marker signal output by an interferometer of the optical receiver is above a threshold value. The control logic may further be configured to adjust, based on the identification, a thermo-optic phase tuner of the interferometer, wherein adjustment of the thermo-optic phase tuner results in a change to the amplitude of the optical marker signal. Other embodiments may be described and/or claimed.

公开(公告)号：US20210325701A1

公开(公告)日：2021-10-21

申请号：US17360160

申请日：2021-06-28

Applicant: INTEL CORPORATION

Inventor： Taehwan Kim ,  Ganesh Balamurugan ,  Hao Li

IPC: G02F1/01

Abstract: Embodiments include apparatuses, methods, and systems including a dynamic polarization controller (DPC) to receive a first light beam and a second light beam, to adjust a rotation of a state of polarization (SOP) of the first light beam and the second light beam to generate a third light beam and a fourth light beam, under the control of a first control signal, a second control signal, and a third control signal. The first control signal may be related to a phase difference between the third light beam and the fourth light beam, the second control signal may be related to an intensity difference between the third light beam and the fourth light beam, and the third control signal may be related to a rotation of a SOP of the third light beam and the fourth light beam. Other embodiments may also be described and claimed.

公开(公告)号：US20210320652A1

公开(公告)日：2021-10-14

申请号：US17357456

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US11126581B2

公开(公告)日：2021-09-21

申请号：US16882408

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Tzu-Chien Hsueh ,  Ganesh Balamurugan ,  Bryan K. Casper

IPC: G06F13/40 ,  G06F1/18 ,  H04L25/02 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/36 ,  G06F13/20 ,  G06F13/42

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.