公开(公告)号：US20200220030A1

公开(公告)日：2020-07-09

申请号：US16641222

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US20240405433A1

公开(公告)日：2024-12-05

申请号：US18328107

申请日：2023-06-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georg Seidemann ,  Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Tae Young Yang

IPC: H01Q9/04 ,  H01Q1/22

Abstract: Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.

公开(公告)号：US20240322775A1

公开(公告)日：2024-09-26

申请号：US18187001

申请日：2023-03-21

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Peter Baumgartner ,  Steven Callender ,  Richard Geiger ,  Harald Gossner ,  Jonathan Jensen

IPC: H03F3/60 ,  H01L23/66 ,  H03F3/195 ,  H03F3/24

CPC classification number: H03F3/602 ,  H01L23/66 ,  H03F3/195 ,  H03F3/245 ,  H01L2223/6677 ,  H03F2200/294 ,  H03F2200/451

Abstract: Disclosed herein are electronic assemblies, integrated circuit (IC) packages, and communication devices implementing three-dimensional power combiners. An electronic assembly may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. Each die includes a first face and an opposing second face, and the second die is stacked above the first die so that the first face of the second die is coupled to the second face of the first die. The electronic assembly further includes a first conductive pathway between one end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between one end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the other ends of the first and second transmission lines.

公开(公告)号：US20230207464A1

公开(公告)日：2023-06-29

申请号：US17552683

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: IC devices including IC devices including BPRs that form metal-semiconductor junctions with semiconductor sections where the BPRs are partially buried are disclosed. An example IC device includes a first layer comprising semiconductor structures, such as fins, nanowires, or nanoribbons. The IC device also includes a layer comprising an electrically conductive material and coupled to the semiconductor structures. The IC device further includes a support structure comprising a BPR and a semiconductor section. The BPR contacts with the semiconductor section and forms a metal-semiconductor junction. The metal-semiconductor junction constitutes a Schottky barrier for electrons. The IC device may include a SCR including a sequence of p-well, n-well, p-well, and n-well with Schottky barriers in the first p-well and the second n-well. The Schottky barrier may also be used as a guard ring to extract injected charge carriers.

公开(公告)号：US20230163120A1

公开(公告)日：2023-05-25

申请号：US17530618

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L27/02 ,  H01L29/868 ,  H01L29/872 ,  H01L29/66

CPC classification number: H01L27/0296 ,  H01L27/0255 ,  H01L29/868 ,  H01L29/872 ,  H01L29/66143 ,  H01L29/66136

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include diodes arranged so that their first and second terminals may be contacted from the opposite faces of a support structure. Such diodes are referred to herein as “vertical diodes” to reflect the fact that the diode extends, in a vertical direction (i.e., in a direction perpendicular to the support structure), between the bottom and the top of support structures. Vertical diodes as described herein may introduce additional degrees of freedom in diode choices in terms of, e.g., high-voltage handling, capacitance modulation, and speed.

公开(公告)号：US11424354B2

公开(公告)日：2022-08-23

申请号：US16642867

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170084578A1

公开(公告)日：2017-03-23

申请号：US15367645

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Sven Albers ,  Michael Skinner ,  Hans-Joachim Barth ,  Peter Baumgartner ,  Harald Gossner

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/552 ,  H01L27/02 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564 ,  H01L23/66 ,  H01L24/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16105 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48482 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/85801 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.

公开(公告)号：US20240364002A1

公开(公告)日：2024-10-31

申请号：US18139206

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/50 ,  H01Q1/2283 ,  H01Q9/045

Abstract: An antenna device includes integrated polymer nanocomposite (PNC) devices coupling an antenna on a substrate to both ground and signal terminals. The PNC devices may include PNC material between two electrodes. The PNC devices may be integrated into the antenna device with the substrate including at least one electrode of each of the PNC devices. One PNC device may convey a signal to or from the antenna, e.g., between the antenna and a signal terminal. Another PNC device may convey an electrostatic discharge (ESD) pulse to a ground terminal. The antenna device may include or be coupled to an integrated circuit (IC) die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US20230178542A1

公开(公告)日：2023-06-08

申请号：US17540609

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Richard Geiger

IPC: H01L27/02 ,  H01L23/48

CPC classification number: H01L27/0292 ,  H01L27/0288 ,  H01L23/481 ,  H01L27/0886

Abstract: IC structures including BPRs used for ESD ballasting are disclosed. An IC structure includes semiconductor structures of one or more transistors. A semiconductor structure may be a fin, nanowire, or nanoribbon of a semiconductor material. The IC structure also includes an electrically conductive layer coupled to the semiconductor structures, a power rail, and a support structure. The power rail is coupled to the electrically conductive layer by a via. The power rail is buried in a support structure. The combination of the power rail and the via constitutes a ESD ballasting resistor for the semiconductor structures. A resistance of the ESD ballasting resistor can be in a range from 5 to 20 ohms. The IC structure may include two or more power rails. A power rail may be arranged between two of the semiconductor structures. The power rails may form a meander structure with other components of the IC structure.

公开(公告)号：US20230068318A1

公开(公告)日：2023-03-02

申请号：US17459986

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Luis Felipe Giles ,  Peter Baumgartner ,  Harald Gossner ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L29/207 ,  H01L29/20 ,  H01L27/06 ,  H01L29/66

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.