公开(公告)号：US20230189659A1

公开(公告)日：2023-06-15

申请号：US17550663

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Tanay A. Gosavi ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14

CPC classification number: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14 ,  G06F7/58

Abstract: A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.

公开(公告)号：US20230065198A1

公开(公告)日：2023-03-02

申请号：US17465752

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Kaan Oguz ,  Punyashloka Debashis

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/02 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32

Abstract: A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

公开(公告)号：US20250006841A1

公开(公告)日：2025-01-02

申请号：US18345127

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Rachel A. Steinhardt ,  Punyashloka Debashis ,  Kevin P. O'Brien ,  Matthew V. Metz ,  Scott B. Clendenning ,  Brandon Holybee ,  Marko Radosavljevic ,  Ian Alexander Young ,  I-Cheng Tung ,  Sudarat Lee ,  Raseong Kim ,  Pratyush P. Buragohain

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/221 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

公开(公告)号：US20250006839A1

公开(公告)日：2025-01-02

申请号：US18343203

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  Rachel A. Steinhardt ,  Pratyush P. Buragohain ,  John J. Plombon ,  Hai Li ,  Gauri Auluck ,  I-Cheng Tung ,  Tristan A. Tronic ,  Dominique A. Adams ,  Punyashloka Debashis ,  Raseong Kim ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Marko Radosavljevic ,  Uygar E. Avci ,  Ian Alexander Young ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230284538A1

公开(公告)日：2023-09-07

申请号：US17685053

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Chia-Ching Lin ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/06 ,  H01L27/22 ,  H01L43/14 ,  H01F10/32 ,  G11C11/18 ,  G11C11/16 ,  H03K19/18

CPC classification number: H01L43/06 ,  H01L27/228 ,  H01L43/14 ,  H01F10/3286 ,  H01F10/3268 ,  G11C11/18 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/18 ,  H01L43/10

Abstract: A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

公开(公告)号：US20230077177A1

公开(公告)日：2023-03-09

申请号：US17469320

申请日：2021-09-08

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Tanay A. Gosavi ,  Ian Alexander Young

IPC: H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L25/10

Abstract: A spin orbit logic (SOL) device includes a first electrically conductive layer; a layer comprising a ferroelectric material (FE layer) on the first electrically conductive layer; a second electrically conductive layer on the FE layer; and a spin orbit coupling (SOC) stack including a first layer (SOC1 layer) including a first SOC material, and a second layer (SOC2 layer) including a second SOC material, the SOC1 layer adjacent the FE layer.

公开(公告)号：US20230070486A1

公开(公告)日：2023-03-09

申请号：US17467124

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Hai Li

IPC: G11C11/16 ,  G06F7/58 ,  G06F17/16

Abstract: Technologies for non-uniform random number generation are disclosed. In one embodiment, the distribution of resistance of a magnetic tunnel junction (MTJ) can be controlled by applying a mechanical strain with a piezoelectric layer and by applying a spin torque by a spin-orbit torque layer. The distribution of resistance can be approximately a Gaussian distribution. In another embodiment, an array of N probabilistic bits (p-bits) has a bias and feedback matrix that result in the array of p-bits outputting an N-bit random number with a non-uniform distribution, such as a Gaussian distribution.

公开(公告)号：US20230068950A1

公开(公告)日：2023-03-02

申请号：US17405953

申请日：2021-08-18

Applicant: Intel Corporation

Inventor： Dmitri Evgenievich Nikonov ,  Hai Li ,  Ian Alexander Young

IPC: H01L29/78 ,  H01L29/10 ,  H03K19/00

Abstract: A leakage insensitive transistor includes a substrate, a source region, a drain region, a channel region between the source region and drain region, a gate dielectric on the channel region, first and second electrodes on the gate dielectric, and third and fourth electrodes on the substrate. The leakage insensitive transistor may be operated by applying a first logic signal to the first electrode, floating the second electrode of the FET, applying a second logic signal opposite the first logic signal to the third electrode, and floating the fourth electrode. A logic circuit may include multiple leakage insensitive transistors.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20250006791A1

公开(公告)日：2025-01-02

申请号：US18346227

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dominique A. Adams ,  Gauri Auluck ,  Pratyush P. Buragohain ,  Scott B. Clendenning ,  Punyashloka Debashis ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.