公开(公告)号：US20200286686A1

公开(公告)日：2020-09-10

申请号：US16296082

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US10565138B2

公开(公告)日：2020-02-18

申请号：US16146534

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jack Kavalieros ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Gregory Chen ,  Van Le ,  Amrita Mathuriya ,  Abhishek Sharma ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Sumbul ,  Ian Young

IPC: G11C8/00 ,  G06F13/16 ,  H01L25/18 ,  H03K19/21 ,  G11C11/408 ,  H01L23/522 ,  G11C11/419

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US10319646B2

公开(公告)日：2019-06-11

申请号：US15498280

申请日：2017-04-26

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L27/092 ,  H01L29/205 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/8258

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US09947780B2

公开(公告)日：2018-04-17

申请号：US15229079

申请日：2016-08-04

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  G06F1/16 ,  G06F1/18 ,  H01L29/04 ,  H01L29/10 ,  H01L29/205 ,  H03F3/195 ,  H03F3/213 ,  H01L29/40 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.

公开(公告)号：US09748391B2

公开(公告)日：2017-08-29

申请号：US15442087

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L29/45 ,  H01L29/207 ,  H01L29/51 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US09698265B2

公开(公告)日：2017-07-04

申请号：US15045666

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/20 ,  H01L29/775 ,  B82Y99/00

CPC classification number: H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

Abstract: Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

公开(公告)号：US09666492B2

公开(公告)日：2017-05-30

申请号：US14798380

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: H01L21/82 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/78

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20160284847A1

公开(公告)日：2016-09-29

申请号：US15179884

申请日：2016-06-10

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L29/267 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L29/207 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US09368583B2

公开(公告)日：2016-06-14

申请号：US14702608

申请日：2015-05-01

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/201 ,  H01L29/06 ,  H01L29/207 ,  H01L29/10 ,  H01L29/51 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20150129830A1

公开(公告)日：2015-05-14

申请号：US13996850

申请日：2013-03-15

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Kelin Kuhn ,  Seiyon Kim ,  Jack Kavalieros ,  Willy Rachmady

IPC: H01L29/10 ,  H01L21/033 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: B41N10/04 ,  B41F3/46 ,  B41F17/08 ,  B41N2210/04 ,  B41N2210/14 ,  H01L21/0332 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  Y10T156/10

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract translation: 本描述的纳米线器件可以在制造至少一个纳米线晶体管期间结合至少一个硬掩模来产生，以便有助于保护最上面的通道纳米线不受制造工艺（例如使用的那些）造成的损伤 在替代金属栅极工艺和/或纳米线释放工艺中。 使用至少一个硬掩模可能导致多层纳米线晶体管中基本上无损的最上通道纳米线，这可以提高通道纳米线的均匀性和整个多层纳米线晶体管的可靠性。