公开(公告)号：US20190036010A1

公开(公告)日：2019-01-31

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian MAERTZ ,  Christopher J. WIEGAND ,  Daniel G. OEULLETTE ,  MD Tofizur RAHMAN ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Tahir GHANI ,  Brian S. DOYLE ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Kaan OGUZ

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US20190027679A1

公开(公告)日：2019-01-24

申请号：US16070415

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Christopher J. WIEGAND ,  MD Tofizur RAHMAN ,  Brian MAERTZ ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Tahir GHANI ,  Mark L. DOCZY

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.

公开(公告)号：US20190140166A1

公开(公告)日：2019-05-09

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahhir GHANI ,  Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20190027537A1

公开(公告)日：2019-01-24

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Oleg GOLONZKA ,  MD Tofizur RAHMAN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Tahir GHANI ,  Satyarth SURI

IPC: H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01L23/528 ,  H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768 ,  H01F41/32

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/32 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/226 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of dielectric layer above a substrates, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20180248116A1

公开(公告)日：2018-08-30

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Satyarth SURI ,  Tejaswi K. INDUKURI

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01F41/34 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/34 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20170345476A1

公开(公告)日：2017-11-30

申请号：US15503359

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Kaan OGUZ ,  Brian S. DOYLE ,  Charles C. KUO ,  Robert S. CHAU ,  Satyarth SURI

IPC: G11C11/16 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12 ,  H01F10/32

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20170323972A1

公开(公告)日：2017-11-09

申请号：US15660574

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Robert S. CHAU ,  Suman DATTA ,  Jack KAVALIEROS ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew METZ

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/267 ,  H01L29/207 ,  H01L29/45 ,  H01L29/51 ,  H01L29/16

CPC classification number: H01L29/201 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.