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    METHOD AND APPARATUS FOR PERFORMING ERROR HANDLING OPERATIONS USING ERROR SIGNALS
    12.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING ERROR HANDLING OPERATIONS USING ERROR SIGNALS 审中-公开
    使用错误信号执行错误处理操作的方法和装置

    公开(公告)号：US20160210187A1

    公开(公告)日：2016-07-21

    申请号：US15080577

    申请日：2016-03-24

    Applicant: INTEL CORPORATION

    Inventor： Bill NALE ,  Jonathan C. JASPER ,  Murugasamy K. NACHIMUTHU ,  Jun ZHU ,  Tuan M. QUACH

    IPC: G06F11/07

    Abstract: Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

    Abstract translation: 提供了一种用于使用误差信号执行错误处理操作的方法和装置。第一错误信号在总线上的错误引脚上被断言，以向主机存储器控制器通知响应于检测到的存储器模块控制器执行错误处理操作 一个错误。 执行错误处理操作以响应于检测到错误将总线返回到初始状态。 在总线上的错误引脚上断言第二个错误信号，表示错误处理操作已经完成，总线返回初始状态。

    ALLOCATING AND CONFIGURING PERSISTENT MEMORY
    13.
    发明申请
    ALLOCATING AND CONFIGURING PERSISTENT MEMORY 审中-公开
    分配和配置持续记忆

    公开(公告)号：US20160179375A1

    公开(公告)日：2016-06-23

    申请号：US14580125

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： SCOTT W. KIRVAN ,  ANDY M. RUDOFF ,  MAHESH S. NATU ,  Murugasamy K. NACHIMUTHU

    IPC: G06F3/06 ,  G11C14/00

    CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/2542 ,  G06F2212/7204 ,  G11C5/04 ,  Y02D10/13

    Abstract: Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes. One or more volumes (visible to an application or operating system) are formed from one or more of the plurality of partitions. Each of the one or more volumes includes one or more of the plurality of partitions having at least one similar attribute from the one or more attributes. In another embodiment, memory controller logic configures a Non-Volatile Memory (NVM) Dual Inline Memory Module (DIMM) into a persistent region and a volatile region. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了分配和/或配置持久存储器的方法和装置。 在一个实施例中，存储器控制器逻辑至少部分地基于一个或多个属性将非易失性存储器配置成多个分区。 一个或多个卷（对应用或操作系统可见）由多个分区中的一个或多个形成。 所述一个或多个卷中的每一个包括所述多个分区中的一个或多个具有来自所述一个或多个属性的至少一个相似属性。 在另一个实施例中，存储器控制器逻辑将非易失性存储器（NVM）双列直插存储器模块（DIMM）配置为持久区域和易失性区域。 还公开并要求保护其他实施例。

    FIRMWARE UPDATE TECHNOLOGIES
    14.
    发明公开
    FIRMWARE UPDATE TECHNOLOGIES 审中-公开

    公开(公告)号：US20240248702A1

    公开(公告)日：2024-07-25

    申请号：US18289558

    申请日：2021-08-03

    Applicant: Intel Corporation

    Inventor： Murugasamy K. NACHIMUTHU ,  Yidong WU ,  Jiaxin WU ,  Ruixia LI

    IPC: G06F8/65

    CPC classification number: G06F8/65

    Abstract: It includes updating firmware on a device during operation of the device by: migrating a service executing on the device for execution on a second device; causing the device to enter a disabled state; storing the firmware for access by the device; and causing the device to reset, wherein the device reset comprises the device executing the stored firmware. It can include selecting a device to operate as a boot strap processor, wherein the selected device is one of a group of devices that are to execute the updated firmware and wherein the boot strap processor performs the causing the device to enter a disabled state, storing the firmware for access by the device, and causing the device to reset. The group of devices can comprise a group of threads within a central processing unit (CPU) socket. The group of devices can comprise central processing units (CPUs) within a CPU package.

    RUNTIME FIRMWARE ACTIVATION FOR MEMORY DEVICES
    17.
    发明申请
    RUNTIME FIRMWARE ACTIVATION FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190243637A1

    公开(公告)日：2019-08-08

    申请号：US16369161

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Shamanna M. DATTA

    IPC: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F3/06

    CPC classification number: G06F8/656 ,  G06F3/0614 ,  G06F3/0632 ,  G06F3/0673 ,  G06F8/654 ,  G06F9/4401

    Abstract: An interface is provided to update a firmware of a persistent memory module at runtime without restarting an operating system on the platform. The operating system initiates the firmware update by triggering a sleep state or by entering a soft reboot. The interface is capable of preserving the state of the platform for all memory modes that support volatile memory regions, persistent memory regions, or both, and reducing or eliminating the demand for access to memory during the firmware update. The persistent memory module is capable of updating the firmware responsive to a platform instruction generated using the interface, including preserving operational states for memory devices in all memory regions, including memory devices in volatile and persistent memory regions.

    NON VOLATILE MEMORY MODULE FOR RACK IMPLEMENTATIONS
    18.
    发明申请
    NON VOLATILE MEMORY MODULE FOR RACK IMPLEMENTATIONS 审中-公开

    公开(公告)号：US20190042511A1

    公开(公告)日：2019-02-07

    申请号：US16023047

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Murugasamy K. NACHIMUTHU ,  Mark A. SCHMISSEUR ,  Dimitrios ZIAKAS ,  Debendra DAS SHARMA ,  Mohan J. KUMAR

    IPC: G06F13/40 ,  G06F13/16 ,  G06F12/02

    Abstract: An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

    CLOUD-BASED SCALE-UP SYSTEM COMPOSITION
    20.
    发明公开
    CLOUD-BASED SCALE-UP SYSTEM COMPOSITION 审中-公开

    公开(公告)号：US20230176919A1

    公开(公告)日：2023-06-08

    申请号：US18103739

    申请日：2023-01-31

    Applicant: Intel Corporation

    Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Krishna Bhuyan

    IPC: G06F9/50 ,  G06F11/07 ,  G06F11/30 ,  H05K7/14

    CPC classification number: G06F9/505 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/3006 ,  G06F11/3055 ,  H05K7/1487 ,  H05K7/1491 ,  G06F11/3034 ,  G06F11/3409

    Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

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