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11.发明申请APPARATUSES, METHODS, AND SYSTEMS FOR JITTER EQUALIZATION AND PHASE ERROR DETECTION 审中-公开用于抖动均衡和相位错误检测的装置，方法和系统公开(公告)号：US20160241223A1
公开(公告)日：2016-08-18
申请号：US15019764
申请日：2016-02-09
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
CPC classification number: H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
Abstract translation: 实施例包括用于抖动均衡和相位误差检测的装置，方法和系统。 在实施例中，通信电路可以包括用于传递数据信号和时钟路径以传递时钟信号的数据路径。 抖动均衡器可以与数据路径和/或时钟路径耦合以分别向数据信号和/或时钟信号提供可编程延迟。 可以通过训练处理来确定延迟，其中可以通过调制频率来调制电源电压。 延迟可以取决于电源电压的值，例如电源电压的电压电平和/或抖动频率分量。 还描述了可以与通信电路和/或其他实施例一起使用的相位误差检测器。
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公开(公告)号：US09735765B2
公开(公告)日：2017-08-15
申请号：US15019764
申请日：2016-02-09
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
CPC classification number: H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
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公开(公告)号：US20170025953A1
公开(公告)日：2017-01-26
申请号：US15188205
申请日：2016-06-21
Applicant: Intel Corporation
Inventor： Nicholas P. COWLEY , Harish K. Krishnamurthy , Ruchir Saraswat
IPC: H02M3/158 , H01L25/065 , H02M1/088 , H02M3/157
CPC classification number: H02M3/158 , H01L25/0657 , H01L2225/06541 , H02M1/088 , H02M3/157 , H02M2001/008
Abstract: Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word.
Abstract translation: 描述了一种装置，其包括：要耦合到第一负载的第一桥; 用于驱动第一桥的第一脉宽调制（PWM）电路; 耦合到第二负载的第二桥; 以及驱动所述第二桥的第二PWM电路，其中所述第一PWM电路由与第二数字字分离的第一数字字来控制，其中所述第二PWM电路由所述第二数字控制，并且其中所述第二数字字被导出 从第一个数字字。
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公开(公告)号：US09502359B2
公开(公告)日：2016-11-22
申请号：US15008230
申请日：2016-01-27
Applicant: INTEL CORPORATION
Inventor： Nicholas P. Cowley , Ruchir Saraswat
IPC: H01L21/44 , H01L23/552 , H01L23/60 , H01L23/13 , H01L23/66 , H01L21/768
CPC classification number: H01L23/552 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/60 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2223/6677 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06537 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/014 , H01L2924/00014
Abstract: Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed.
Abstract translation: 本文公开了屏蔽装置的实施例。 在一些实施例中，屏蔽装置可以包括第一和第二导电区域以及设置在第一和第二导电区域之间的多个通孔。 第一和第二导电区域和多个通孔可以围绕集成电路（IC）部件，并且多个通孔中的各个通孔相对于彼此间隔开以屏蔽进入或输出的电磁干扰（EMI）。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20160066818A1
公开(公告)日：2016-03-10
申请号：US14481375
申请日：2014-09-09
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Ruchir Saraswat , Richard J. Goldman
CPC classification number: A61B5/6807 , A43B3/0005 , A43B17/00 , A61B5/1038 , A61B5/112 , A61B2560/0214 , A61B2562/0247 , A61B2562/028 , A61B2562/12 , A61B2562/164 , A61B2562/166 , A61B2562/187
Abstract: Embodiments of the present disclosure provide techniques and configurations for an orthotic device. In one instance, the device may include an orthotic device body and at least two sensors spatially disposed inside the orthotic device body. A first sensor may provide a first output responsive to pressure resulting from application of mechanical force to the orthotic device body. A second sensor may provide a second output responsive to flexing resulting from the application of mechanical force to the orthotic device body. The device may also include a control unit communicatively coupled with the sensors to receive and process the outputs provided by the sensors in response to pressure and flexing. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例提供了用于矫正装置的技术和配置。 在一个实例中，该装置可以包括矫正装置主体和空间地设置在矫正装置主体内的至少两个传感器。 第一传感器可以提供响应于对矫正装置主体施加机械力而产生的压力的第一输出。 第二传感器可以提供响应于由机械力施加到矫正装置主体而产生的弯曲的第二输出。 该装置还可以包括与传感器通信地耦合的控制单元，以响应于压力和弯曲来接收和处理由传感器提供的输出。 可以描述和/或要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US10290598B2
公开(公告)日：2019-05-14
申请号：US15323521
申请日：2014-08-07
Applicant: Intel Corporation
Inventor： Kevin J. Lee , Ruchir Saraswat , Uwe Zillmann , Nicholas P. Cowley , Richard J. Goldman
IPC: H01L23/00 , H01F27/28 , G06F1/16 , H01L23/64 , H01L23/522 , H03H9/64 , H03H7/42 , H01L23/48 , H01L23/66 , H01L23/525
Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.
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公开(公告)号：US10013025B2
公开(公告)日：2018-07-03
申请号：US14567581
申请日：2014-12-11
Applicant: INTEL CORPORATION
Inventor： Nicholas P. Cowley , Ruchir Saraswat , Richard Goldman , Ryan Palmer
CPC classification number: G06F1/163 , G06F1/1635 , G06F1/26 , G06F1/3206 , G06F1/3215 , G06F3/0414 , H01L41/113 , H02N2/181
Abstract: Embodiments of the present disclosure provide techniques and configurations for a wearable device with power state control. In one instance, the device a functional module to operate in a first power state or in a second power state that is different from the first power state; a power source coupled with the functional module to provide operational power to the functional module; and a power state control module coupled with the functional module, to cause the functional module to transition from the first power state to the second power state in response to an input. The power state control module may comprise a power generating device to generate power responsive to the input, independent of the power source, and in response to the generated power, cause the functional module to transition from the first power state to the second power state. Other embodiments may be described and/or claimed.
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公开(公告)号：US09948186B2
公开(公告)日：2018-04-17
申请号：US15188205
申请日：2016-06-21
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Harish K. Krishnamurthy , Ruchir Saraswat
CPC classification number: H02M3/158 , H01L25/0657 , H01L2225/06541 , H02M1/088 , H02M3/157 , H02M2001/008
Abstract: Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word.
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公开(公告)号：US20170245035A1
公开(公告)日：2017-08-24
申请号：US15502495
申请日：2014-09-17
Applicant: Intel Corporation
Inventor： Kevin J. Lee , Ruchir Saraswat , Uwe Zillmann , Valluri Bob Rao , Tor Lund-Larsen , Nicholas P. Cowley
CPC classification number: H04R1/04 , B81B7/02 , B81B2201/0257 , B81B2207/096 , B81C1/00158 , B81C2201/0132 , B81C2203/0109 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/131 , H01L2224/16227 , H01L2224/27002 , H01L2224/27618 , H01L2224/27848 , H01L2224/29011 , H01L2224/2919 , H01L2224/3201 , H01L2224/32058 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/83005 , H01L2224/83193 , H01L2224/83438 , H01L2224/8346 , H01L2224/83488 , H01L2224/8359 , H01L2224/83688 , H01L2224/83862 , H01L2224/92 , H01L2224/9222 , H01L2224/92225 , H01L2924/1461 , H01L2924/15311 , H01L2924/161 , H01L2924/16151 , H01L2924/16152 , H01L2924/163 , H01L2924/166 , H04R1/406 , H04R19/005 , H04R19/04 , H01L2924/014 , H01L2924/0665 , H01L2924/01014 , H01L2924/00014 , H01L2924/00012 , H01L2224/11 , H01L2224/27 , H01L2224/83 , H01L2224/81 , H01L2221/68304
Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.
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公开(公告)号：US09645646B2
公开(公告)日：2017-05-09
申请号：US14477122
申请日：2014-09-04
Applicant: Intel Corporation
Inventor： Nicholas P Cowley , Richard J Goldman , Ruchir Saraswat
IPC: G06F3/01 , G06F3/0346
CPC classification number: G06F3/016
Abstract: A device to output two or more coordinated haptic effects, comprising, a first haptic effect generator to output a first haptic effect, a second haptic effect generator to output a second haptic effect and a processor to coordinate operation of the second haptic effect generator with operation of the first haptic effect generator based on an input provided to the processor.
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