公开(公告)号：US20200235216A1

公开(公告)日：2020-07-23

申请号：US16630143

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H03F3/193

Abstract: Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion.

公开(公告)号：US20190393319A1

公开(公告)日：2019-12-26

申请号：US16016391

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/51 ,  H01L21/285

Abstract: A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.

公开(公告)号：US20190259806A1

公开(公告)日：2019-08-22

申请号：US16347724

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Paul FISCHER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Edris MOHAMMED

IPC: H01L27/20 ,  H03H3/08 ,  H03H9/02 ,  H03H9/10 ,  H03H9/145 ,  H03H9/25

Abstract: A surface acoustic wave (SAW) resonator structure, an integrated circuit, and a method of fabricating a SAW structure are provided. The method includes epitaxially growing a crystalline aluminum nitride piezoelectric film layer on a substrate; and deposing a plurality of electrodes on the piezoelectric film layer. The SAW structure includes a substrate, a piezoelectric film on the substrate, and a plurality of electrodes on the piezoelectric film.

公开(公告)号：US20190181099A1

公开(公告)日：2019-06-13

申请号：US16302420

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L23/552 ,  H01P3/00 ,  H01L23/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66 ,  H01P11/00

CPC classification number: H01L23/552 ,  H01L21/8252 ,  H01L23/5225 ,  H01L23/66 ,  H01L27/0605 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2223/6627 ,  H01P3/003 ,  H01P11/003

Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).

公开(公告)号：US20190172938A1

公开(公告)日：2019-06-06

申请号：US16258422

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20180219087A1

公开(公告)日：2018-08-02

申请号：US15505911

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20170256408A1

公开(公告)日：2017-09-07

申请号：US15604550

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz K. GARDNER ,  Pragyansri PATHI ,  Matthew V. METZ ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  James M. POWERS ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: G06Q30/02

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US20170186598A1

公开(公告)日：2017-06-29

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20160181099A1

公开(公告)日：2016-06-23

申请号：US14908987

申请日：2013-09-04

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz K. GARDNER ,  Pragyansri PATHI ,  Matthew V. METZ ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  James M. POWERS ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/267

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (I) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

Abstract translation: 提供沟槽（以及用于形成沟槽的工艺），其从衬底材料的顶表面减少或防止III-V族或锗（Ge）材料（例如，“缓冲材料”）的选择性外延生长中的晶体缺陷。 缺陷可能由选择性外延侧壁生长与氧化物沟槽侧壁的碰撞引起。 这种沟槽包括（I）相对于衬底表面以40度至70度（例如55度）之间的角度具有倾斜侧壁的沟槽; 和/或（2）具有在下沟槽的开口上方并且围绕下沟槽（例如，下沟槽可以具有倾斜侧壁，短垂直壁或高垂直壁）的上沟槽的组合沟槽。 这些沟槽减少或防止外延侧壁生长中的缺陷，其中生长与其生长的沟槽的垂直侧壁接触或生长。

公开(公告)号：US20160163918A1

公开(公告)日：2016-06-09

申请号：US14906542

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. Chau ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER

IPC: H01L33/06 ,  H01L33/62 ,  H01L33/20 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L27/153 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/16 ,  H01L33/20 ,  H01L33/32 ,  H01L33/325 ,  H01L33/62 ,  H01L2933/0033

Abstract: Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.

Abstract translation: 描述了在硅鳍模板上形成III-V LED结构的方法。 这些方法和结构可以包括在硅鳍片的硅（111）面上形成n掺杂的III-V层，在n掺杂的III-V层上形成量子阱层，形成p掺杂的III-V 层，然后在p掺杂的III-V层上形成欧姆接触层。