公开(公告)号：US20210125992A1

公开(公告)日：2021-04-29

申请号：US16645362

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Shem O. OGADHOH ,  Yih WANG ,  Bernhard SELL ,  Allen GARDINER ,  Blake LIN ,  Juan G. ALZATE VINASCO ,  Pei-Hua WANG ,  Chieh-Jen KU ,  Abhishek A. SHARMA

IPC: H01L27/108 ,  H01L27/12

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393223A1

公开(公告)日：2019-12-26

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Yih WANG ,  Shriram SHIVARAMAN

IPC: H01L27/108 ,  H01L27/13 ,  G11C11/4096 ,  G11C11/408 ,  H01L29/786 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L21/311 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24 ,  H01L29/22

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US20180342277A1

公开(公告)日：2018-11-29

申请号：US16052552

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Liqiong WEI ,  Fatih HAMZAOGLU ,  Yih WANG ,  Nathaniel J. AUGUST ,  Blake C. LIN ,  Cyrille DRAY

IPC: G11C11/16 ,  G11C13/00 ,  G11C29/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2213/74 ,  G11C2213/79

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20170229166A1

公开(公告)日：2017-08-10

申请号：US15496655

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Yih WANG ,  Muhammad M. KHELLAH ,  Fatih HAMZAOGLU

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

公开(公告)号：US20160232968A1

公开(公告)日：2016-08-11

申请号：US15025229

申请日：2013-12-05

Applicant: INTEL CORPORATION

Inventor： Nathaniel J. AUGUST ,  Pulkit JAIN ,  Stefan RUSU ,  Fatih HAMZAOGLU ,  Rangharajan VENKATESAN ,  Muhammad KHELLAH ,  Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ ,  Yih WANG

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract translation: 描述了一种包括使用电阻性存储器保持的存储单元的装置。 该装置包括：存储元件，包括交叉耦合到第二反相器件的第一反相器件; 具有至少一个电阻性存储器元件的恢复电路，所述恢复电路耦合到所述第一反相器件的输出; 耦合到所述第一反相装置的输出的第三反相装置; 耦合到第三反相装置的输出的第四反相装置; 以及具有至少一个电阻性存储器元件的保存电路，所述保存电路耦合到所述第三反相器件的输出端。

公开(公告)号：US20160125927A1

公开(公告)日：2016-05-05

申请号：US14129277

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Liqiong WEI ,  Fatih HAMZAOGLU ,  Yih WANG ,  Nathaniel J. AUGUST ,  Blake C. LIN ,  Cyrille DRAY

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2213/74 ,  G11C2213/79

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

Abstract translation: 描述了用于提高电阻式存储器能量效率的装置。 一种装置执行数据驱动写入，以利用write0和write1操作之间的非对称写入开关能量。 该装置包括：耦合到位线和选择线的电阻存储器单元; 耦合到位线的第一通过栅极; 耦合到所述选择线的第二通过栅极; 以及可由输入数据操作的多路复用器，用于根据输入数据的逻辑电平向第一和第二传递门提供控制信号或写入驱动器。 一种装置包括用于在写入操作之前执行读取的电路，其避免了利用初始低功率读取操作的不必要的写入。 一种装置包括执行自动写入操作的电路，其一旦位单元翻转就停止写入操作。 一种装置包括用于执行自动读取操作的电路，其在检测到数据时停止读取操作。

公开(公告)号：US20200227472A1

公开(公告)日：2020-07-16

申请号：US16831658

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Tahir GHANI ,  Joseph M. STEIGERWALD ,  John H. EPPLE ,  Yih WANG

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US20190393356A1

公开(公告)日：2019-12-26

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Miriam RESHOTKO ,  Matthew METZ ,  Yih WANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Abhishek SHARMA ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L23/522 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304897A1

公开(公告)日：2019-10-03

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L27/108

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20190013353A1

公开(公告)日：2019-01-10

申请号：US16067801

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Oleg GOLONZKA ,  Tahir GHANI ,  Ruth A. BRAIN ,  Yih WANG

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L23/532 ,  G11C11/16 ,  H01L23/522

Abstract: Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.