公开(公告)号：US09997609B2

公开(公告)日：2018-06-12

申请号：US15068958

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/417 ,  H01L21/285 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02 ,  H01L21/321 ,  H01L23/532 ,  H01L23/535 ,  H01L29/51 ,  H01L29/78 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L29/49 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

公开(公告)号：US09735248B2

公开(公告)日：2017-08-15

申请号：US15248002

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/16 ,  H01L29/40 ,  H01L29/41 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/48 ,  H01L21/768 ,  H01L21/225 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/167 ,  H01L21/285 ,  H01L23/485

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US09728537B2

公开(公告)日：2017-08-08

申请号：US15219910

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/78 ,  H01L29/10 ,  H01L29/04 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US20170047331A1

公开(公告)日：2017-02-16

申请号：US15202940

申请日：2016-07-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

公开(公告)号：US20170033188A1

公开(公告)日：2017-02-02

申请号：US15248095

申请日：2016-08-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/40 ,  H01L21/3065 ,  H01L29/45 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract translation: 半导体器件包括设置在衬底上的栅极; 栅极的相对侧上的源极区域和漏极区域; 以及在所述源极区域和所述漏极区域中的至少一个的界面层部分上方并邻接一对沟槽接触部; 其中所述界面层包括在约5×10 21至约5×102 2原子/ cm 2范围内的量的硼。

公开(公告)号：US20160336321A1

公开(公告)日：2016-11-17

申请号：US15219910

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/033

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US09484256B1

公开(公告)日：2016-11-01

申请号：US14964917

申请日：2015-12-10

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/00 ,  H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/417 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract translation: 半导体器件包括设置在衬底上的栅极; 栅极的相对侧上的源极区域和漏极区域; 以及在所述源极区域和所述漏极区域中的至少一个的界面层部分上方并邻接一对沟槽接触部; 其中所述界面层包括在约5×10 21至约5×102 2原子/ cm 2范围内的量的硼。

公开(公告)号：US20160211342A1

公开(公告)日：2016-07-21

申请号：US15068958

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/49 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

Abstract translation: 描述了形成金属 - 绝缘体半导体（MIS）接触的方法，包括MIS接触的晶体管和MIS接触。 该方法包括蚀刻用于形成接触的开口，该开口延伸到半导体区域的上表面。 该方法还包括在半导体区域的上表面内的选定深度处注入金属离子，并将半导体区域的上表面转换为金属氧化物绝缘层。 该方法还包括在绝缘层上形成金属层。

公开(公告)号：US20250077804A1

公开(公告)日：2025-03-06

申请号：US18458141

申请日：2023-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ankur Agrawal ,  Andrea Fasoli ,  Monodeep Kar ,  Kyu-hyoun Kim ,  Sergey Rylov ,  Chia-Yu Chen ,  Xiao Sun

IPC: G06G7/32

Abstract: A first circuit is configured to split a first integer value into a first coarse value and a first fine value, and split a second integer value into a second coarse value and a second fine value. A second circuit performs an analog multiply and accumulate (MAC) operation on the first and second coarse values to produce a first analog output, perform an analog MAC operation on the first coarse value and the second fine value to produce a second analog output, perform an analog MAC operation on the first fine value and the second coarse value to produce a third analog output, and perform an analog MAC operation on the first and second fine values together to produce a fourth analog output. A third circuit is configured to perform analog-to-digital (A/D) conversion on and combine the analog output signals to produce a reconstructed digital output signal.

公开(公告)号：US12061991B2

公开(公告)日：2024-08-13

申请号：US17029506

申请日：2020-09-23

Applicant: International Business Machines Corporation ,  National Tsing Hua University

Inventor： Pin-Yu Chen ,  Sijia Liu ,  Chia-Yu Chen ,  I-Hsin Chung ,  Tsung-Yi Ho ,  Yun-Yun Tsai

IPC: G06N3/094 ,  G06N3/08 ,  G06N3/096 ,  G06N20/00 ,  G06F18/213 ,  G06F18/2134 ,  G06F18/214

CPC classification number: G06N3/094 ,  G06N3/08 ,  G06N3/096 ,  G06N20/00 ,  G06F18/213 ,  G06F18/21347 ,  G06F18/214

Abstract: Transfer learning in machine learning can include receiving a machine learning model. Target domain training data for reprogramming the machine learning model using transfer learning can be received. The target domain training data can be transformed by performing a transformation function on the target domain training data. Output labels of the machine learning model can be mapped to target labels associated with the target domain training data. The transformation function can be trained by optimizing a parameter of the transformation function. The machine learning model can be reprogrammed based on input data transformed by the transformation function and a mapping of the output labels to target labels.