公开(公告)号：US10297671B2

公开(公告)日：2019-05-21

申请号：US16040978

申请日：2018-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee ,  Vijay Narayanan ,  Koji Watanabe

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66

Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.

公开(公告)号：US10297598B2

公开(公告)日：2019-05-21

申请号：US15406985

申请日：2017-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul Jamison ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.

公开(公告)号：US10283610B2

公开(公告)日：2019-05-07

申请号：US15894246

申请日：2018-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ULVAC, Inc.

Inventor： Vijay Narayanan ,  Yohei Ogawa ,  John Rozen

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

公开(公告)号：US10217745B2

公开(公告)日：2019-02-26

申请号：US15959832

申请日：2018-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/8258 ,  H01L21/28

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

公开(公告)号：US20180330996A1

公开(公告)日：2018-11-15

申请号：US16026209

申请日：2018-07-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US20180197972A1

公开(公告)日：2018-07-12

申请号：US15911892

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/28 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09984940B1

公开(公告)日：2018-05-29

申请号：US15418916

申请日：2017-01-30

Applicant: International Business Machines Corporation ,  ULVAC, Inc.

Inventor： Jack O. Chu ,  Stephen M. Gates ,  Masanobu Hatanaka ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Yohei Ogawa ,  John Rozen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L21/845 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28008 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/28264 ,  H01L23/298 ,  H01L23/3171 ,  H01L23/3192 ,  H01L27/1211 ,  H01L29/785

Abstract: A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SixH(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.

公开(公告)号：US09960252B2

公开(公告)日：2018-05-01

申请号：US15258597

申请日：2016-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US20180076040A1

公开(公告)日：2018-03-15

申请号：US15262206

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/51

CPC classification number: H01L21/28255 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02255 ,  H01L29/161 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US20180006108A1

公开(公告)日：2018-01-04

申请号：US15198800

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Vijay Narayanan ,  Adam M. Pyzyna

IPC: H01L49/02 ,  H01L21/02

CPC classification number: H01L28/75

Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.