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    Fabricating polysilicon MOS devices and passive ESD devices
    14.
    发明授权
    Fabricating polysilicon MOS devices and passive ESD devices 有权
    制造多晶硅MOS器件和无源ESD器件

    公开(公告)号：US08951893B2

    公开(公告)日：2015-02-10

    申请号：US13733243

    申请日：2013-01-03

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC: H01L27/04 ,  H01L21/36 ,  H01L21/84 ,  H01L27/12

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

    Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

    Abstract translation: 描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。 沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。 导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。 介电层沉积在导电层顶上，并且通孔形成在电介质层中。 另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。 另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。 然后通过排气孔去除上部和下部硅牺牲膜。

    OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES
    19.
    发明申请
    OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES 有权
    具有多级光学波长的光电结构和形成结构的方法

    公开(公告)号：US20150277064A1

    公开(公告)日：2015-10-01

    申请号：US14224210

    申请日：2014-03-25

    Applicant: International Business Machines Corporation

    Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

    IPC: G02B6/42 ,  G02B6/136 ,  G02B6/132 ,  G02B6/122

    CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

    Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

    Abstract translation: 公开了具有光波导的结构，该光波导具有第一级的第一段和在第一级和高级第二级之间延伸并且还沿第二级延伸的第二段。 具体地，波导包括在第一和第二介电层之间的第一段。 第二电介质层具有沟槽，该沟槽延伸到第一电介质层，并且其一侧位于与第一段的端部横向相邻的位置。 波导还包括从沟槽的底部在与第一部分相邻的一侧上延伸直到并沿着沟槽相对侧上的第二电介质层的顶表面延伸的第二部分。 第三介电层覆盖沟槽中的第二段和第二介电层的顶表面。 还公开了形成这种光电子结构的方法。

    SEMICONDUCTOR CHIP WITH A DUAL DAMASCENE WIRE AND THROUGH-SUBSTRATE VIA (TSV) STRUCTURE
    20.
    发明申请
    SEMICONDUCTOR CHIP WITH A DUAL DAMASCENE WIRE AND THROUGH-SUBSTRATE VIA (TSV) STRUCTURE 有权
    具有双重DAMASCENE线和通过基底（TSV）结构的半导体芯片

    公开(公告)号：US20150194345A1

    公开(公告)日：2015-07-09

    申请号：US14146788

    申请日：2014-01-03

    Applicant: International Business Machines Corporation

    Inventor： Fen Chen ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin S. Petrarca ,  Anthony K. Stamper

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2224/13

    Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

    Abstract translation: 公开了一种具有双镶嵌绝缘线和绝缘的穿通基板通孔（TSV）结构的半导体芯片以及形成芯片的方法。 所述方法包括双镶嵌技术，其中沟槽和通孔开口形成在衬底上方的电介质层中，使得沟槽位于第一通孔上方，并且通孔开口定位成与第一通孔相邻并且从沟槽垂直延伸并进入 基质。 电介质间隔物形成在沟槽和通孔开口的侧壁上。 沉积金属层以在沟槽中形成绝缘电线，并在通孔开口中形成绝缘的TSV。 因此，绝缘线将绝缘TSV与第一通孔电连接，从而将其连接到下面的片上器件或下部金属级线。 随后，将衬底变薄以暴露衬底底部的绝缘TSV。

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