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公开(公告)号：US09405618B2
公开(公告)日：2016-08-02
申请号：US14289311
申请日：2014-05-28
Applicant: Infineon Technologies AG
Inventor： Thomas Rabenalt , Ulrich Backhausen , Thomas Kern , Michael Goessel
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C16/10 , G11C16/26 , G11C29/52 , G11C2029/0411 , H03M13/13
Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
Abstract translation: 公开了一种用于访问非易失性存储器的方法和存储器控制器。 该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储区域确定的所得到的纠错数据没有影响。 该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个 第二存储器区域以及第二存储器区域是否可写入。
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公开(公告)号：US20140198583A1
公开(公告)日：2014-07-17
申请号：US13743409
申请日：2013-01-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Thomas Nirschl
CPC classification number: G11C16/14 , G11C16/0433 , G11C16/0466 , G11C16/10 , G11C16/24 , G11C16/26
Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.
Abstract translation: 实施例涉及包括多个非易失性存储器元件的系统和方法，其中至少两个非易失性存储器元件的集合共享一个选择元件，用于选择用于读取操作的非易失性存储器元件组中的特定一个的非易失性存储器元件之一， 一个程序操作。
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公开(公告)号：US10319460B2
公开(公告)日：2019-06-11
申请号：US13966679
申请日：2013-08-14
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Thomas Nirschl
IPC: G11C29/50 , G11C16/34 , G06F11/16 , G11B20/18 , G06F11/10 , G11C29/02 , G11C29/42 , G11C29/52 , G11C16/28
Abstract: A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts.
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公开(公告)号：US10067826B2
公开(公告)日：2018-09-04
申请号：US15194089
申请日：2016-06-27
Applicant: Infineon Technologies AG
Inventor： Thomas Rabenalt , Ulrich Backhausen , Thomas Kern , Michael Goessel
Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
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公开(公告)号：US20170256315A1
公开(公告)日：2017-09-07
申请号：US15447466
申请日：2017-03-02
Applicant: Infineon Technologies AG
Inventor： Ulrich Backhausen , Giacomo Curatolo , Jens Rosenbusch
CPC classification number: G11C13/0097 , G01R31/1227 , G01R31/14 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2013/0083 , G11C2029/5006 , G11C2213/79
Abstract: A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.
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Patent Agency Ranking
公开(公告)号：US20160306696A1
公开(公告)日：2016-10-20
申请号：US15194089
申请日：2016-06-27
Applicant: Infineon Technologies AG
Inventor： Thomas Rabenalt , Ulrich Backhausen , Thomas Kern , Michael Goessel
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C16/10 , G11C16/26 , G11C29/52 , G11C2029/0411 , H03M13/13
Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
Abstract translation: 公开了一种用于访问非易失性存储器的方法和存储器控制器。 该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储器区域确定的所得到的纠错数据没有影响。 该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个 第二存储器区域以及第二存储器区域是否可写入。
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17.发明申请Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error 有权用于校正包含相邻2位错误的3位错误的电路和方法公开(公告)号：US20140173386A1
公开(公告)日：2014-06-19
申请号：US13720780
申请日：2012-12-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Thomas Kern , Ulrich Backhausen , Thomas Rabenalt , Christian Badack , Michael Goessel
IPC: H03M13/15
CPC classification number: H03M13/152 , H03M13/1575 , H03M13/616
Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′1, . . . , v′n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n′ column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.
Abstract translation: 提出了用于校正可能错误的二进制字v'= v'1中的错误的电路。 。 。 ，v'n相对于码字v = v1，。 。 。 ，vn，特别是包含相邻2位错误（突发错误）的3位错误。 电路包括校正子发生器和解码器。 使用修改的BCH，其中第一BCH码子矩阵的n个列向量作为列向量对配对，使得每个列向量对的两个列向量的分量XOR组合产生与所有列不同的相同列向量K 第一个BCH子矩阵的向量。 第二BCH子矩阵包括根据第一BCH子矩阵中的列向量的伽罗瓦域算术的作为第三功率的相应的列向量。 可以针对第一和第二子矩阵的列检查由发生器产生的综合征。
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公开(公告)号：US10599350B2
公开(公告)日：2020-03-24
申请号：US15955327
申请日：2018-04-17
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Ulrich Backhausen
Abstract: A method is suggested for updating a memory comprising a first memory area and a second memory area, the method comprising the steps: (a) using a first image of data that is stored in the first memory area while writing a second image of data to the second memory area; (b) switching to using the second image of data that is stored in the second memory area; (c) writing an inverse image of the second image to the first memory area; and (d) using the first memory area and the second memory area as a differential memory. Also, a corresponding device is provided.
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公开(公告)号：US20180307424A1
公开(公告)日：2018-10-25
申请号：US15955327
申请日：2018-04-17
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Ulrich Backhausen
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0679 , G06F8/654 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0408 , G11C16/10 , G11C16/28 , G11C2013/0042
Abstract: A method is suggested for updating a memory comprising a first memory area and a second memory area, the method comprising the steps: (a) using a first image of data that is stored in the first memory area while writing a second image of data to the second memory area; (b) switching to using the second image of data that is stored in the second memory area; (c) writing an inverse image of the second image to the first memory area; and (d) using the first memory area and the second memory area as a differential memory. Also, a corresponding device is provided.
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公开(公告)号：US09343179B2
公开(公告)日：2016-05-17
申请号：US14132053
申请日：2013-12-18
Applicant: Infineon Technologies AG
Inventor： Thomas Nirschl , Jens Rosenbusch , Ulrich Backhausen , Thomas Kern , Thomas Liebermann
CPC classification number: G11C29/024 , G06F11/1076
Abstract: A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.
Abstract translation: 公开了一种执行三次扫描以测试地址解码器和字线驱动电路的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。
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