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    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)
    14.
    发明授权
    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
    为芯片上的系统（SoC）提供外围组件互连（PCI）兼容的事务级别协议，

    公开(公告)号：US09547618B2

    公开(公告)日：2017-01-17

    申请号：US14262158

    申请日：2014-04-25

    Applicant: INTEL CORPORATION

    Inventor： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/36 ,  G06F13/40 ,  G06F13/38

    CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能 无需修改即可并入设备。 描述和要求保护其他实施例。

    Reducing latency of unified memory transactions
    16.
    发明授权
    Reducing latency of unified memory transactions 有权
    减少统一内存事务的延迟

    公开(公告)号：US09489322B2

    公开(公告)日：2016-11-08

    申请号：US14317308

    申请日：2014-06-27

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Prashanth Kalluraya

    IPC: H03M13/00 ,  G06F13/16 ,  G06F13/42 ,  H04L1/18

    CPC classification number: G06F13/1631 ,  G06F13/4234 ,  H04L1/1867

    Abstract: In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，装置包括消耗逻辑，用于请求和处理包括关键数据部分和第二数据部分的数据，所述数据存储在耦合到插入在所述装置和所述存储器之间的处理器的存储器中。 此外，该装置包括耦合到消费逻辑的协议栈逻辑，以经由处理器向存储器发出读请求，以响应于读请求来请求数据并接收多个完成。 在一个实施例中，协议栈逻辑包括完成处理逻辑，用于在完成之后完成协议栈处理之前将第一个完成的数据发送到消费逻辑。 描述和要求保护其他实施例。

    Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
    17.
    发明申请
    Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints 审中-公开
    用于提高根端口和根端口集成端点恢复时间的方法，设备和系统

    公开(公告)号：US20160209911A1

    公开(公告)日：2016-07-21

    申请号：US14998158

    申请日：2015-12-24

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Robert E. Gough

    IPC: G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/325 ,  G06F9/4418 ,  G06F13/42 ,  H04L49/15 ,  Y02D10/151 ,  Y02D50/20

    Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

    Abstract translation: 芯片上的系统（SoC）具有多核处理器，二级（L2）高速缓存控制器，二级高速缓存，集成存储器控制器和串行点到点链路接口，以实现多核之间的通信 处理器和设备。 该接口实现协议栈，并且包括发送器，用于向设备发送串行数据，接收器反序列化输入串行流。 协议栈支持多个功率管理状态，包括其中向设备提供电源电压的有效状态，第一关闭状态和不提供电源电压的第二关闭状态 到设备。 响应于设备准备进入活动状态的指示，协议栈提供在默认恢复时间到期之前访问设备以完成转换。

    LOW POWER ENTRY IN A SHARED MEMORY LINK
    18.
    发明申请
    LOW POWER ENTRY IN A SHARED MEMORY LINK 有权
    共享存储器链接中的低电源输入

    公开(公告)号：US20160179427A1

    公开(公告)日：2016-06-23

    申请号：US14576125

    申请日：2014-12-18

    Applicant: Intel Corporation

    Inventor： Michelle C. Jen ,  Debendra Das Sharma ,  Mahesh Wagh ,  Venkatraman Iyer

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F1/3234 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/385

    Abstract: Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.

    Abstract translation: 根据存储器访问链路协议，数据被发送以对应于通过链路与共享存储器相关联的加载/存储类型操作，并且存储器访问链路协议将被覆盖在另一不同的链路协议上。 发送请求进入低功率状态，其中请求包括在令牌的字段中编码的数据值，令牌是指示分组数据的开始，并且进一步指示是否在后发送的后续数据 令牌是根据其他链路协议和存储器访问链路协议之一来包括数据。

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