公开(公告)号：US09224878B2

公开(公告)日：2015-12-29

申请号：US13727962

申请日：2012-12-27

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

IPC: H01L21/20 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52 ,  H01L51/00

CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

公开(公告)号：US20150137315A1

公开(公告)日：2015-05-21

申请号：US14599843

申请日：2015-01-19

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

公开(公告)号：US20140227871A1

公开(公告)日：2014-08-14

申请号：US14257694

申请日：2014-04-21

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一种情况下，形成在电介质区域上的覆盖层材料随后可以被去除，从而确保覆盖层材料仅在导电区域上形成。 硅烷类材料可用于形成掩模层。 覆盖层可以由导电材料，半导体材料或绝缘材料形成，并且可以使用包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积的任何适当的工艺形成。

公开(公告)号：US20130320495A1

公开(公告)日：2013-12-05

申请号：US13738510

申请日：2013-01-10

Applicant: INTERMOLECULAR, INC.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L29/92

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

公开(公告)号：US08575036B2

公开(公告)日：2013-11-05

申请号：US13676981

申请日：2012-11-14

Applicant: Intermolecular, Inc.

Inventor： David E. Lazovsky ,  Thomas R. Boussie ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  B82Y30/00 ,  H01L21/02183 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76849

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在由电介质区域分离的导电区域上形成覆盖层时，掩模层阻止在电介质区域上或电介质区域中形成覆盖层材料。 可以选择性地在导电区域或非选择性地形成覆盖层; 可以去除在电介质区域上形成的覆盖层材料，从而确保仅在导电区域上形成覆盖层材料。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由半导体材料或电绝缘材料的导电材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺，例如无电沉积，化学气相沉积，物理气相沉积或原子层沉积 。

公开(公告)号：US20130244425A1

公开(公告)日：2013-09-19

申请号：US13892516

申请日：2013-05-13

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

公开(公告)号：US20130122683A1

公开(公告)日：2013-05-16

申请号：US13738865

申请日：2013-01-10

Applicant: Intermolecular Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

公开(公告)号：US20130119512A1

公开(公告)日：2013-05-16

申请号：US13665524

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L29/92

CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02356 ,  H01L27/10852 ,  H01L28/75

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 金属氧化物第二电极层形成在电介质层的上方。 金属氧化物第二电极层具有与电介质层的晶体结构相容的晶体结构。 可选地，在金属氧化物第二电极层上形成第二电极体层。

公开(公告)号：US20130095632A1

公开(公告)日：2013-04-18

申请号：US13708035

申请日：2012-12-07

Applicant: Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Pragati Kumar ,  Sandra G. Malhotra

IPC: H01L21/02

CPC classification number: H01L21/02 ,  B82Y99/00 ,  C01G23/047 ,  C01P2002/72 ,  C23C16/0272 ,  C23C16/34 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02186 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US20130072026A1

公开(公告)日：2013-03-21

申请号：US13676981

申请日：2012-11-14

Applicant: INTERMOLECULAR, INC.

Inventor： David E. Lazovsky ,  Thomas R. Boussie ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  B82Y30/00 ,  H01L21/02183 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76849

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在由电介质区域分离的导电区域上形成覆盖层时，掩模层阻止在电介质区域上或电介质区域中形成覆盖层材料。 可以选择性地在导电区域或非选择性地形成覆盖层; 可以去除在电介质区域上形成的覆盖层材料，从而确保仅在导电区域上形成覆盖层材料。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由半导体材料或电绝缘材料的导电材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺，例如无电沉积，化学气相沉积，物理气相沉积或原子层沉积 。