公开(公告)号：US5049967A

公开(公告)日：1991-09-17

申请号：US631907

申请日：1990-12-21

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US20050101097A1

公开(公告)日：2005-05-12

申请号：US11000092

申请日：2004-12-01

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/20 ,  H01L21/8222

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US6133094A

公开(公告)日：2000-10-17

申请号：US123405

申请日：1998-07-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US5512497A

公开(公告)日：1996-04-30

申请号：US272312

申请日：1994-07-08

申请人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

发明人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265 ,  H01L21/8238

CPC分类号： H01L21/28026 ,  H01L21/28525 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

摘要翻译： 公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

公开(公告)号：US5508549A

公开(公告)日：1996-04-16

申请号：US735948

申请日：1991-07-25

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US4984200A

公开(公告)日：1991-01-08

申请号：US271309

申请日：1988-11-15

申请人： Ryuichi Saitoo ,  Osamu Saitoo ,  Takahide Ikeda ,  Mitsuru Hirao ,  Atsushi Hiraishi

发明人： Ryuichi Saitoo ,  Osamu Saitoo ,  Takahide Ikeda ,  Mitsuru Hirao ,  Atsushi Hiraishi

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： G11C11/412 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S257/906

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.

摘要翻译： 这里公开了一种包括SRAM的半导体集成电路器件，SRAM由具有高电阻负载元件的存储单元和通过导电层与触发器电路的信息存储节点连接的电源电压线组成。 在与通过电介质膜形成在信息存储节的部分上的导电层上形成电容元件的平板电极层相同的制造步骤中，用于屏蔽数据线的场效应的电场屏蔽膜是 通过层间绝缘膜形成在高电阻负载元件上。

公开(公告)号：US4963973A

公开(公告)日：1990-10-16

申请号：US323212

申请日：1989-03-13

申请人： Atsuo Watanabe ,  Yoshiaki Yazawa ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma

发明人： Atsuo Watanabe ,  Yoshiaki Yazawa ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0623 ,  H01L21/8238 ,  H01L21/8249 ,  Y10S257/921

摘要： A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

摘要翻译： 半导体器件具有在衬底的表面中形成的阱区，并且在阱区中形成有诸如MOSFET和双极晶体管的半导体元件。 阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置 底物。 优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。

公开(公告)号：US4578693A

公开(公告)日：1986-03-25

申请号：US505447

申请日：1983-06-17

申请人： Yoshiaki Yazawa ,  Nobuaki Miyakawa ,  Toji Mukai ,  Takahide Ikeda ,  Tatsuya Kamei

发明人： Yoshiaki Yazawa ,  Nobuaki Miyakawa ,  Toji Mukai ,  Takahide Ikeda ,  Tatsuya Kamei

IPC分类号： H01L27/146 ,  H01L31/0216 ,  H01L31/10 ,  H01L27/14 ,  H01L31/00

CPC分类号： H01L27/14643 ,  H01L31/02164

摘要： In a semiconductive photodetector device having a semiconductor substrate and a plurality of photodiodes juxtaposed in one major surface of the semiconductor substrate, exposed edges of adjacent pn junctions of adjacent photodiodes are covered with a polysilicon film.

摘要翻译： 在具有半导体衬底和并置在半导体衬底的一个主表面上的多个光电二极管的半导体光电检测器件中，相邻光电二极管的相邻pn结的暴露边缘被多晶硅膜覆盖。

公开(公告)号：US4089020A

公开(公告)日：1978-05-09

申请号：US677807

申请日：1976-04-16

申请人： Takahide Ikeda ,  Michio Ishikawa

发明人： Takahide Ikeda ,  Michio Ishikawa

IPC分类号： H01L21/265 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01L21/26513 ,  H01L29/872

摘要： A semiconductor diode consists of a low resistivity n conductivity type semiconductor substrate, a high resistivity n conductivity type semiconductor layer, formed on the surface of the substrate, a high resistivity p conductivity type semiconductor layer, whose thickness is smaller than the diffusion length of electrons, formed on the n conductivity type layer, a metal electrode forming a Schottky barrier contact with the p conductivity type layer, and an electrode forming an ohmic contact with the substrate.

摘要翻译： 半导体二极管由形成在基板表面上的低电阻率n导电型半导体基板，高电阻率n导电型半导体层，厚度小于电子扩散长度的高电阻率p导电型半导体层构成 形成在n导电型层上的金属电极，与p导电型层形成肖特基势垒接触的金属电极，以及与基板形成欧姆接触的电极。

公开(公告)号：US06740958B2

公开(公告)日：2004-05-25

申请号：US10115101

申请日：2002-04-04

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。