公开(公告)号：US08502367B2

公开(公告)日：2013-08-06

申请号：US12893651

申请日：2010-09-29

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H01L23/495

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00

Abstract: An electronic package that includes a composite material base. In one embodiment the electronic package is an expanded wafer-level package. The composite material base is composed of woven strands and polymer material. In one embodiment the composite material base is composed of woven fiberglass strands and an epoxy material. In various embodiments the package includes an electronic circuitry layer on one or another face of the composite material base. In other embodiments conductive vias connect the circuitry layers, including a redistribution layer. In yet another embodiment an electronic package is mounted on the composite material base and electrically couples to the circuit of the expanded wafer-level package. The package having the composite material base is mechanically stronger and can be made thinner than a package that relies on an encapsulant material for structure, and resists cracking.

Abstract translation: 一种包括复合材料基底的电子封装。 在一个实施例中，电子封装是扩展的晶片级封装。 复合材料基底由编织线和聚合物材料组成。 在一个实施方案中，复合材料基底由编织的玻璃纤维束和环氧材料组成。 在各种实施例中，封装包括在复合材料基底的一个或另一个面上的电子电路层。 在其它实施例中，导电通孔连接电路层，包括再分配层。 在另一个实施例中，电子封装安装在复合材料基底上并电耦合到扩展的晶片级封装的电路。 具有复合材料基底的包装机械地更坚固，并且可以制成比依赖于用于结构的密封剂材料的包装，并且抗龟裂。

公开(公告)号：US20100148363A1

公开(公告)日：2010-06-17

申请号：US12336273

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/49816 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls.

Abstract translation: 球栅阵列（BGA）封装包括具有第一侧和第二侧的衬底层。 半导体芯片通过介电粘合剂层附接到基板层的第一侧。 多个焊球附着在基板层的第二面上。 焊球可以由行和列排列。 多个电线将半导体芯片电连接到焊球。 一层封装化合物沉积在半导体芯片上。 在密封化合物层的边缘或周边处或附近，在封装化合物层中形成所选择的深度和形状的台阶腔。 阶跃腔通过衬底层与焊球分离，但跨越多个选定的焊球。

公开(公告)号：US20100148347A1

公开(公告)日：2010-06-17

申请号：US12336422

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/043 ,  H01L23/52 ,  H01L21/02

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20130170164A1

公开(公告)日：2013-07-04

申请号：US13340345

申请日：2011-12-29

Applicant: Jing-En Luan ,  Hk Looi

Inventor： Jing-En Luan ,  Hk Looi

IPC: H05K7/06 ,  H05K3/30 ,  H05K1/16

CPC classification number: H05K3/305 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/09781 ,  H05K2201/09909 ,  Y02P70/613 ,  Y10T29/4913

Abstract: On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate.

Abstract translation: 在其上使用粘合剂将电子或结构部件耦合到基板的电路基板上，设置粘合剂阻挡层以防止粘合剂干扰电路的操作。 可以在选定的位置提供接触垫并具有选定的形状，并将焊料沉积在垫上，然后回流以形成坝。 大坝可以是焊接到接触垫的结构，或者可以通过设备的另一种结构在其端部处支撑坝，使得在其用于容纳粘合剂的位置处，该坝不附着到基底。

公开(公告)号：US08466997B2

公开(公告)日：2013-06-18

申请号：US12651304

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H04N5/225 ,  H05K7/00 ,  H01L23/06

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals. The solder balls and the semiconductor substrate are at least partially encapsulated in an encapsulating layer formed on the face of the transparent substrate, which has been planarized to expose upper portions of the solder balls, as contact pads of the optical sensor package.

Abstract translation: 光学传感器封装具有在其表面上形成有再分布层的透明衬底，其包括窗口和多个导电迹线。 包括光学传感器和其表面上的多个接触端子的半导体衬底以与光学传感器直接相对的窗口面对面布置在透明衬底上，并且每个接触端子 电耦合到相应的一个导电端子。 透明基板具有比半导体基板更大的总体尺寸，使得透明基板的一个或多个边缘延伸超过半导体基板的对应边缘。 多个焊球定位在透明基板的表面上，每个焊球与相应的导电端子电接触。 焊球和半导体衬底至少部分地封装在形成在透明衬底的已被平坦化以暴露焊球上部的表面上的封装层中，作为光学传感器封装的接触焊盘。

公开(公告)号：US20110156240A1

公开(公告)日：2011-06-30

申请号：US12651362

申请日：2009-12-31

Applicant: Jing-En Luan ,  Kim-Yong Goh

Inventor： Jing-En Luan ,  Kim-Yong Goh

IPC: H01L23/488 ,  H01L21/78 ,  H01L21/60

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/03 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A fan-out wafer level package includes a semiconductor die with contact pads positioned on a top surface. A fan-in redistribution layer positioned over the die includes contact pads in electrical communication with the first contact pads of the die. A buffer layer positioned over the fan-in layer includes a plurality of vias, in electrical contact with the contact pads of the fan-in layer. A fan-in redistribution layer is positioned over the buffer layer and includes contact pads on a surface opposite the buffer layer, in electrical communication with the vias. The semiconductor die, fan-in layer, and buffer layer are encapsulated in a molding com-pound layer. Solder contacts, for electrically connecting the semiconductor device to a electronic circuit board, are positioned on contact pads of the fan-out layer. The buffer layer has a substantial thickness, to reduce and distribute shear stresses resulting from thermal mismatch of coefficients of thermal expansion of the semiconductor die and a circuit board.

Abstract translation: 扇形晶片级封装包括具有位于顶表面上的接触焊盘的半导体管芯。 位于管芯上方的扇形重分布层包括与管芯的第一接触垫电连通的接触焊盘。 位于扇入层之上的缓冲层包括与扇入层的接触垫电接触的多个通孔。 风扇再分配层位于缓冲层上方，并且包括与通孔相通的与缓冲层相对的表面上的接触焊盘。 将半导体管芯，扇入层和缓冲层封装在成型层中。 用于将半导体器件电连接到电子电路板的焊接触点位于扇出层的接触焊盘上。 缓冲层具有相当大的厚度，以减少和分配由半导体管芯和电路板的热膨胀系数的热失配导致的剪切应力。

公开(公告)号：US07956475B2

公开(公告)日：2011-06-07

申请号：US12336273

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/28

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/49816 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls.

Abstract translation: 球栅阵列（BGA）封装包括具有第一侧和第二侧的衬底层。 半导体芯片通过介电粘合剂层附接到基板层的第一侧。 多个焊球附着在基板层的第二面上。 焊球可以由行和列排列。 多个电线将半导体芯片电连接到焊球。 一层封装化合物沉积在半导体芯片上。 在密封化合物层的边缘或周边处或附近，在封装化合物层中形成所选择的深度和形状的台阶腔。 阶跃腔通过衬底层与焊球分离，但跨越多个选定的焊球。

公开(公告)号：US20100327421A1

公开(公告)日：2010-12-30

申请号：US12495515

申请日：2009-06-30

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/4899 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A protective structure is provided on a substrate to which a semiconductor die is attached. The protective structure surrounds the die and reduces the thermo-mechanical stresses to which the die is subject. The die is protected against cracking, warping, and delamination.

Abstract translation: 在安装有半导体管芯的基板上设置保护结构。 保护结构围绕模具并降低模具所受到的热机械应力。 该模具可防止开裂，翘曲和分层。

公开(公告)号：US09640574B2

公开(公告)日：2017-05-02

申请号：US13029665

申请日：2011-02-17

Applicant: Jing-En Luan ,  Junyong Chen

Inventor： Jing-En Luan ,  Junyong Chen

IPC: H01L27/146 ,  H04N5/225

CPC classification number: H01L27/14618 ,  H01L2224/48091 ,  H01L2224/73265 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00014

Abstract: A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material.

公开(公告)号：US08389335B2

公开(公告)日：2013-03-05

申请号：US13424610

申请日：2012-03-20

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L21/00

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。