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39 条记录 (耗时 0.032 秒)

    Dielectric structure and method of formation
    11.
    发明授权
    Dielectric structure and method of formation 失效
    介电结构和形成方法

    公开(公告)号：US06495239B1

    公开(公告)日：2002-12-17

    申请号：US09458291

    申请日：1999-12-10

    申请人： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

    发明人： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

    IPC分类号： B32B310

    CPC分类号： B32B7/04 ,  B32B27/26 ,  B32B27/32 ,  B32B2250/40 ,  B32B2305/72 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/28 ,  Y10T428/31511

    摘要： A dielectric structure, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured and nonadhesively coupled to one of the fully cured PID layers. The dialectric structure may further include a second PID film partially cured and nonadhesively coupled to the other fully cured PID layer.

    摘要翻译： 一种电介质结构，其中该结构的两个完全固化的可光成像电介质（PID）层通过部分固化的PID层非粘性地接合。 部分固化的PID层包括夹在第一部分固化的PID片和第二部分固化的PID片之间的动力平面。 完全固化的PID层各自包括内部电源平面，具有导电耦合到内部电源平面的盲端的电镀通孔以及穿过完全固化的PID层的电镀通孔。 电介质结构还可以包括部分固化并非粘性地耦合到完全固化的PID层之一的第一PID膜。 所述方程式结构还可以包括部分固化并非粘性地耦合到另一完全固化的PID层的第二PID膜。

    Semi-subtractive circuitization
    12.
    发明授权
    Semi-subtractive circuitization 失效
    半减法电路

    公开(公告)号：US5427895A

    公开(公告)日：1995-06-27

    申请号：US172409

    申请日：1993-12-23

    申请人： Roy H. Magnuson ,  Richard W. Malek ,  Voya R. Markovich ,  William E. Wilson

    发明人： Roy H. Magnuson ,  Richard W. Malek ,  Voya R. Markovich ,  William E. Wilson

    IPC分类号： H05K3/10 ,  H05K3/24 ,  H05K3/42 ,  G03F7/00

    CPC分类号： H05K3/427 ,  H05K3/108 ,  H05K2201/0355 ,  H05K2203/072 ,  H05K3/244

    摘要： A process for selective plating of a metal onto a substrate surface is provided. The process includes laminating a layer of conductive metal onto a dielectric substrate; and providing thru holes extending through said layer of conductive metal and said dielectric substrate.A thin layer of conductive metal is plated on the walls of the thru holes; and a photoresist layer is applied to the surface of the conductive metal and selectively exposed and developed to provide a mask corresponding to the negative of the desired circuit pattern.The exposed metal that is not covered by the photoresist is removed and then the remaining photoresist is removed to thereby provide the desired circuit pattern. A conductive metal is plated on the pattern up to the desired thickness.

    摘要翻译： 提供了将金属选择性镀覆到基板表面上的工艺。 该方法包括将导电金属层层压到电介质基底上; 并且提供穿过所述导电金属层和所述电介质基板的通孔。 导电金属薄层镀在通孔的壁上; 并且将光致抗蚀剂层施加到导电金属的表面并选择性地暴露和显影以提供对应于期望电路图案的负值的掩模。 去除未被光致抗蚀剂覆盖的暴露的金属，然后除去剩余的光致抗蚀剂，从而提供所需的电路图案。 将导电金属镀在图案上达到所需厚度。

    Method of making circuitized substrate with internal optical pathway using photolithography
    14.
    发明授权
    Method of making circuitized substrate with internal optical pathway using photolithography 失效
    使用光刻法制造具有内部光学路径的电路化衬底的方法

    公开(公告)号：US07713767B2

    公开(公告)日：2010-05-11

    申请号：US11907004

    申请日：2007-10-09

    申请人： Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

    发明人： Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

    IPC分类号： H01L21/77 ,  H01L21/00 ,  G02B6/02 ,  G02B6/12 ,  G03G15/00

    CPC分类号： G02B6/43 ,  G02B6/132 ,  G02B6/136 ,  H05K1/0274

    摘要： A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum. The formed substrate is capable of being both optically and electrically coupled to one or more other substrates possessing similar capabilities, thereby forming an electro-optical assembly of such substrates.

    摘要翻译： 一种制造电路化衬底（例如PCB）的方法，其包括至少一个可能的几个内部光学路径作为其一部分，使得所得到的衬底将能够传输和/或接收电信号和光信号。 该方法包括在光学核心的一侧和相邻的直立构件之间形成至少一个开口，使得开口由至少一个角形侧壁限定。 通过光学芯材料（或从上方进入芯体）的光从该角形侧壁反射。 因此，开口内的介质（例如空气）由于其相对于相邻的光学芯材料的反射率而与反射介质一样起作用。 该方法利用了常规PCB制造中使用的许多工艺，从而将成本降至最低。 所形成的基底能够光学和电耦合到具有相似能力的一个或多个其它基底，从而形成这种基底的电光学组件。

    Dielectric structure and method of formation
    16.
    发明授权
    Dielectric structure and method of formation 失效
    介电结构和形成方法

    公开(公告)号：US06699350B2

    公开(公告)日：2004-03-02

    申请号：US10217616

    申请日：2002-08-12

    申请人： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

    发明人： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

    IPC分类号： B32B3100

    CPC分类号： B32B7/04 ,  B32B27/26 ,  B32B27/32 ,  B32B2250/40 ,  B32B2305/72 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/28 ,  Y10T428/31511

    摘要： A method for forming a dielectric structure. A first layer is formed, wherein the first layer includes a first fully cured photoimageable dielectric (PID) material. A sticker lays is nonadhesively formed on the first layer, wherein the sticker layer includes a partially cured PID material. A second layer is nonadhesively formed on the sticker layer, wherein the second layer includes a second fully cured PID material, wherein the sticker layer is nonadhesively sandwiched between the first layer and the second layer such that the sticker layer is in non-adhesive contact with the first layer and in non-adhesive contact with the second layer, and wherein the sticker layer is capable of remaining in non-adhesive contact with the first layer and the second layer until the sticker layer is subsequently subjected to additional curing.

    摘要翻译： 一种形成电介质结构的方法。 形成第一层，其中第一层包括第一完全固化的可光成像的电介质（PID）材料。 在第一层上非粘性地形成贴纸，其中贴纸层包括部分固化的PID材料。 第二层非粘性地形成在粘合剂层上，其中第二层包括第二完全固化的PID材料，其中粘合层非粘性地夹在第一层和第二层之间，使得粘合剂层与 所述第一层与所述第二层非粘合接触，并且其中所述粘合剂层能够保持与所述第一层和所述第二层的非粘合性接触，直到所述粘合剂层随后进行另外的固化。

    Conducting paste for device level interconnects
    18.
    发明授权
    Conducting paste for device level interconnects 有权
    用于器件级互连的导电膏

    公开(公告)号：US08685284B2

    公开(公告)日：2014-04-01

    申请号：US12884657

    申请日：2010-09-17

    申请人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

    发明人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

    IPC分类号： H01B1/00 ,  H01B1/22 ,  H01B1/02

    CPC分类号： H01B1/22 ,  H01L2224/81 ,  Y10T29/49117

    摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

    摘要翻译： 导电糊和形成用于器件级互连的糊的方法。 导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。 通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。 一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。 通常，小于5微米的平均片尺寸适用于五微米互连。 然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。 最终混合物中基于LMP的糊剂的量优选为20-50重量％。 纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

    Circuitized substrate with internal cooling structure and electrical assembly utilizing same
    19.
    发明申请
    Circuitized substrate with internal cooling structure and electrical assembly utilizing same 失效
    具有内部冷却结构的电路化基板和利用其的电气组件

    公开(公告)号：US20090109624A1

    公开(公告)日：2009-04-30

    申请号：US11976468

    申请日：2007-10-25

    申请人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

    发明人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

    IPC分类号： H05K7/20 ,  H05K3/20

    CPC分类号： H05K1/0206 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/44 ,  H05K2201/064 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24917 ,  H01L2924/00

    摘要： An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided.

    摘要翻译： 一种电气组件，其包括电路化衬底，其包括以层叠取向交替取向的第一多个电介质和导电电路层，结合到所述电介质层之一的热冷结构和安装在所述电路化衬底上的至少一个电气部件。 电路化衬底包括位于其中的多个导电和导热通孔，选择的导热通孔热耦合到电气部件并延伸穿过第一多个电介质和导电电路层，并且 热耦合到热冷却结构，这些选择的导热通孔中的每一个在组装操作期间提供从电气部件到热冷却结构的热路径。 热冷却结构适于在组件的操作期间使冷却流体通过。 还提供了制造基板的方法。