Abstract:
To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.
Abstract:
A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.
Abstract:
A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.
Abstract:
A program verification method is for a nonvolatile memory device which programs a plurality of memory cells. The program verification method includes applying a plurality of verification voltages, and determining whether programming of memory cells, having different target threshold voltage distributions, from among the plurality of memory cells is completed based on one of the plurality of verification voltages.
Abstract:
The inventive concept provides optic couplers, optical fiber laser devices, and active optical modules using the same. The optic coupler may include a first optical fiber having a first core and a first cladding surrounding the first core, a second optical fiber having a second core transmitting a signal light to the first optical fiber and a third cladding surrounding the second core, third optical fibers transmitting pump-light to the first optical fiber in a direction parallel to the second optical fiber; and a connector connected between the first optical fiber and the second optical fiber, the connector extending the third optical fibers disposed around the second optical fiber toward the first optical fiber, the connector comprising a third core connected between the first core and the second core and a fifth cladding surrounding the third core.
Abstract:
A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.
Abstract:
A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.
Abstract:
Provided is a mask pattern for selective area growth of a semiconductor layer and a selective area growth method for a semiconductor layer for independently controlling a growth rate and a strain of the semiconductor layer. The selective area growth method includes: forming a plurality of pairs of first mask patterns, the first mask patterns in each pair including a first open area therebetween, the first open area having a width that is wider than a distance causing overgrowth of the semiconductor layer, the pairs of the first mask patterns repeatedly arranged with a period P therebetween; wherein controlling a growth rate and a strain of the semiconductor layer formed on the first open area by adjusting the period P.
Abstract:
To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.
Abstract:
The inventive concept provides optic couplers, optical fiber laser devices, and active optical modules using the same. The optic coupler may include a first optical fiber having a first core and a first cladding surrounding the first core, a second optical fiber having a second core transmitting a signal light to the first optical fiber and a third cladding surrounding the second core, third optical fibers transmitting pump-light to the first optical fiber in a direction parallel to the second optical fiber; and a connector connected between the first optical fiber and the second optical fiber, the connector extending the third optical fibers disposed around the second optical fiber toward the first optical fiber, the connector comprising a third core connected between the first core and the second core and a fifth cladding surrounding the third core.