摘要:
The present invention provides a photodiode comprising a p-i-n or pn junction at least partly formed by first and second regions (2) made of semiconductor materials having opposite conductivity type, wherein the p-i-n or pn junction comprises a light absorption region (11) for generation of charge carriers from absorbed light. One section of the p-i-n or pn junction is comprises by one or more nanowires (7) that are spaced apart and arranged to collect charge carriers generated in the light absorption region (11). At least one low doped region (10) made of a low doped or intrinsic semiconductor material provided between the nanowires (7) and one of said first region (1) and said second region (2) enables custom made light absorption region and/or avalanche multiplication region of the active region (9).
摘要:
Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.
摘要:
The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.
摘要:
In a mobile communications network, drifts in timing of user equipment in soft handover may be accounted for by measuring the offset between the current timing of the user equipment and the first significant path of downlink frames from cells of the active set at first and second instances. Differences in the respective offsets from the first and second instances may be calculated to determine if the drift is unidirectional in time for all cells of the active set. A unidirectional drift in the offsets is indicative of a drift in timing of the user equipment, allowing the current timing to be momentarily unfrozen and updated.
摘要:
A nanostructured device according to the invention comprises a first group of nanowires protruding from a substrate where each nanowire of the first group of nanowires comprises at least one pn- or p-i-n-junction. A first contact, at least partially encloses and is electrically connected to a first side of the pn- or p-i-n-junction of each nanowire in the first group of nanowires. A second contacting means comprises a second group of nanowires that protrudes from the substrate, and is arranged to provide an electrical connection to a second side of the pn- or p-i-n-junction.
摘要:
The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires (1) and applying an electrical field (E) over the population of nanowires (1), whereby an electrical dipole moment of the nanowires makes them align along the electrical field (E). Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate (2). The electrical field can be utilised in the deposition. Pn-junctions or any net charge introduced in the nanowires (1) may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.
摘要:
The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated position with regards to the substrate. A pn-junction is formed by the combination of the bulb and the nanowire resulting in an active region to produce light.
摘要:
Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.
摘要:
The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centers (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centers (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centers (10) alters the conductivity of the nanowire (3).
摘要:
The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.