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    METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE
    11.
    发明申请
    METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE 有权
    在印刷电路基板中形成多层电容器的方法

    公开(公告)号：US20120223047A1

    公开(公告)日：2012-09-06

    申请号：US12909983

    申请日：2010-10-22

    申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    IPC分类号： H01G4/002 ,  G03F7/30 ,  G03F7/20

    CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

    摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

    摘要翻译： 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

    Method of making a circuitized substrate having at least one capacitor therein
    12.
    发明申请
    Method of making a circuitized substrate having at least one capacitor therein 审中-公开
    制造其中具有至少一个电容器的电路化基板的方法

    公开(公告)号：US20080248596A1

    公开(公告)日：2008-10-09

    申请号：US11878673

    申请日：2007-07-26

    申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    IPC分类号： H01L21/77

    CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

    摘要： A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.

    摘要翻译： 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。 在另一个实施例中，可以在沉积在电介质层上的金属层内形成至少两个间隔开的导体，这些导体在其间限定通道。 然后可以在通道内沉积（例如，使用层压）的电容电介质材料。

    Method of forming an electrically conductive printed line
    19.
    发明授权
    Method of forming an electrically conductive printed line 有权
    形成导电印刷线的方法

    公开(公告)号：US08499445B1

    公开(公告)日：2013-08-06

    申请号：US13184699

    申请日：2011-07-18

    申请人： Rabindra N. Das ,  Frank D. Egitto ,  Voya R. Markovich

    发明人： Rabindra N. Das ,  Frank D. Egitto ,  Voya R. Markovich

    IPC分类号： H05K3/40

    CPC分类号： H05K3/246 ,  H05K3/1216 ,  H05K3/125 ,  H05K3/243 ,  H05K2201/0245 ,  H05K2203/0425 ,  H05K2203/072 ,  H05K2203/095 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

    摘要： Printed conductive lines and a method of preparing them using polymer nanocomposites with low resistivity and high current carrying capacity. Plasma treatment selectively removes polymers/organics from nanocomposites. Subsequent selective metal is deposited on top of the exposed metal surface of the printed conductive lines in order to improve current carrying capacity of the conductive printed lines. The printed conductive lines use a conductive ink or printing process and are then cured thermally and/or by a lamination process. Next, the printed conductive lines are treated with the plasma for 5-15 minutes in order to remove organics. E-less copper (Cu) is selectively deposited only at the conducting particle surface of the printed conductive lines. If desired, e-less gold, silver, tin, or tin-lead can be deposited on top of the e-less Cu.

    摘要翻译： 印刷导电线及其使用具有低电阻率和高载流能力的聚合物纳米复合材料制备它们的方法。 等离子体处理选择性地从纳米复合材料中除去聚合物/有机物。 随后的选择性金属沉积在印刷导线的暴露的金属表面的顶部上，以便改善导电印刷线的载流能力。 印刷的导线使用导电油墨或印刷工艺，然后热固化和/或通过层压工艺固化。 接下来，印刷的导线用等离子体处理5-15分钟以除去有机物。 仅在印刷导线的导电粒子表面选择性地沉积无电铜（Cu）。 如果需要，可以在无电镀铜的顶部上沉积无电镀金，银，锡或锡铅。