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    VIA STACK FAULT DETECTION
    13.
    发明申请
    VIA STACK FAULT DETECTION 有权
    通过堆叠故障检测

    公开(公告)号：US20150348647A1

    公开(公告)日：2015-12-03

    申请号：US14291589

    申请日：2014-05-30

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: G11C29/12 ,  G11C29/50

    CPC classification number: G11C29/12005 ,  G11C29/025 ,  G11C2029/5006

    Abstract: A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack.

    Abstract translation: 公开了一种方法和装置。 一种这样的方法包括选择通过通孔堆叠耦合在一起的多个管芯的管芯。 所选芯片上的通孔可以接地。 电源电压耦合到通孔叠层的一端，并测量得到的电流。 将计算的电阻与预期电阻进行比较，以确定通孔堆叠中是否存在故障。

    APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK
    14.
    发明申请
    APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK 有权
    在主/从存储堆栈中进行单元识别的装置和方法

    公开(公告)号：US20140160867A1

    公开(公告)日：2014-06-12

    申请号：US13709792

    申请日：2012-12-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

    IPC: G11C7/00

    CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

    Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

    Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

    POWER REGENERATION IN A MEMORY DEVICE
    15.
    发明申请
    POWER REGENERATION IN A MEMORY DEVICE 有权

    公开(公告)号：US20250040439A1

    公开(公告)日：2025-01-30

    申请号：US18917686

    申请日：2024-10-16

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: H10N19/00 ,  H01L23/00 ,  H01L23/38 ,  H01L29/68 ,  H10N10/01 ,  H10N10/13 ,  H10N10/17

    Abstract: A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.

    TECHNIQUES FOR FLEXIBLE SELF-REFRESH OF MEMORY ARRAYS
    16.
    发明公开
    TECHNIQUES FOR FLEXIBLE SELF-REFRESH OF MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230395116A1

    公开(公告)日：2023-12-07

    申请号：US18202149

    申请日：2023-05-25

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Scott E. Smith

    IPC: G11C11/406

    CPC classification number: G11C11/406

    Abstract: Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.

    Power distribution for stacked memory
    18.
    发明授权
    Power distribution for stacked memory 有权

    公开(公告)号：US11532349B2

    公开(公告)日：2022-12-20

    申请号：US17221498

    申请日：2021-04-02

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Brian P. Callaway

    IPC: G11C11/40 ,  G11C11/4074 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/525 ,  G11C11/22 ,  G06F13/16

    Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

    SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS
    19.
    发明申请
    SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220334917A1

    公开(公告)日：2022-10-20

    申请号：US17854331

    申请日：2022-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: G06F11/10

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

    Determination of durations of memory device temperatures
    20.
    发明授权
    Determination of durations of memory device temperatures 有权

    公开(公告)号：US11449267B1

    公开(公告)日：2022-09-20

    申请号：US17243357

    申请日：2021-04-28

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  Anthony D. Veches

    IPC: G06F3/06

    Abstract: Methods, systems, and apparatuses related to determination of durations of memory device temperatures are described. For example, a controller can be coupled to a memory device to monitor an operating temperature of the memory device. The controller can determine the operating temperature exceeds a threshold temperature. The controller can determine a duration that the temperature exceeds the threshold temperature. The controller can provide data corresponding to the operating temperature and the duration to a requesting device.

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