公开(公告)号：US09293348B2

公开(公告)日：2016-03-22

申请号：US14143040

申请日：2013-12-30

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  Yen-Hao Shih

IPC: H01L23/528 ,  H01L27/105 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/768 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/32133 ,  H01L21/32055 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括基板，堆叠结构，电介质层，导电结构，电介质结构和导电插塞。 堆叠结构包括交替布置的介电膜和导电膜。 介电层位于导电结构和层叠结构的侧壁之间。 电介质结构在堆叠结构上并且限定通孔。 导电插塞填充通孔并物理地接触由通孔暴露并与电介质层相邻的导电膜之一。

公开(公告)号：US09224750B1

公开(公告)日：2015-12-29

申请号：US14296173

申请日：2014-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

IPC: H01L27/10 ,  H01L27/115 ,  H01L29/40

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

Abstract translation: 存储器阵列包括沿着第一方向延伸的多个脊形多层堆叠，以及形成在所述多个脊形多层堆叠的顶部上的硬掩模层。 硬掩模层分别包括与多个脊形多层堆叠垂直对准的多个条带，沿着与第一方向正交的第二方向连接相邻条纹的多个桥，以及多个硬 通过多个桥和多个条之间的孔掩模。

公开(公告)号：US09461064B2

公开(公告)日：2016-10-04

申请号：US14948482

申请日：2015-11-23

Applicant: Macronix International Co., Ltd

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

IPC: H01L21/82 ,  H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

公开(公告)号：US09397209B2

公开(公告)日：2016-07-19

申请号：US13657026

申请日：2012-10-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Yen-Hao Shih

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L29/78 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/32139 ,  H01L27/11524

Abstract: A semiconductor structure has a second portion with an appendage on one side of the second portion and extruding along the longitudinal direction of the second portion. Moreover the semiconductor structure also has a gate line longitudinally parallel to the second portion, wherein the length of the gate line equals to the longitudinal length of the second portion.

Abstract translation: 半导体结构具有第二部分，在第二部分的一侧具有附着物并且沿着第二部分的纵向挤出。 此外，半导体结构还具有纵向平行于第二部分的栅极线，其中栅极线的长度等于第二部分的纵向长度。

公开(公告)号：US09245603B2

公开(公告)日：2016-01-26

申请号：US14058328

申请日：2013-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: G11C7/14 ,  H01L27/115

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

公开(公告)号：US20150357341A1

公开(公告)日：2015-12-10

申请号：US14296173

申请日：2014-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

IPC: H01L27/115 ,  H01L29/40

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

Abstract translation: 存储器阵列包括沿着第一方向延伸的多个脊形多层堆叠，以及形成在所述多个脊形多层堆叠的顶部上的硬掩模层。 硬掩模层分别包括与多个脊形多层堆叠垂直对准的多个条带，沿着与第一方向正交的第二方向连接相邻条纹的多个桥，以及多个硬 通过多个桥和多个条之间的孔掩模。

公开(公告)号：US09136277B2

公开(公告)日：2015-09-15

申请号：US13652701

申请日：2012-10-16

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/11575 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.

Abstract translation: 一种三维堆叠半导体结构，包括：多个氧化物层和交替布置的导电层的堆叠，至少一个与氧化物层和导电层垂直形成的接触孔，并延伸到一个导电层，形成于侧壁 形成在接触孔中并连接相应导电层的导体，并且相应的导电层包括硅化物。 硅化物可以形成在相应导电层的边缘或整个主体上。 除了硅化物之外，相应的导电层可以部分地或完全地还包括连接到导体的导电材料。 接触孔延伸的相应的导电层具有比其它导电层更高的导电性。 此外，3D堆叠半导体结构可以应用于3D闪存的扇出区域。

公开(公告)号：US09076535B2

公开(公告)日：2015-07-07

申请号：US13936729

申请日：2013-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yen-Hao Shih

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578

Abstract: A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions.

Abstract translation: 为存储器提供了基于薄膜晶体管的存储器件中的电荷载体源。 电荷载流子源可以包括具有第一和第二端子的二极管。 经由第一开关耦合到位线的NAND串通过第二开关耦合到第二端，耦合到二极管的第一端。 分别可驱动的第一和第二电源线分别耦合到二极管的第一和第二端子。 包括耦合到第一和第二电源线的电路，其被配置为根据包括正向偏置条件和反向偏置条件的操作模式，以不同的偏置条件偏置第一和第二电源线。

公开(公告)号：US08772747B2

公开(公告)日：2014-07-08

申请号：US13867525

申请日：2013-04-22

Applicant: Macronix International Co., Ltd.

Inventor： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

IPC: H01L47/00

CPC classification number: H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

Abstract translation: 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

公开(公告)号：US09123778B2

公开(公告)日：2015-09-01

申请号：US13897702

申请日：2013-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Guanru Lee

IPC: H01L21/4763 ,  H01L21/8242 ,  H01L29/40 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L21/76808 ,  H01L21/28282 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

Abstract translation: 对于某些三维堆叠的存储器件，用于存储器单元的位线或字线被堆叠成布置成沿第一方向延伸的间隔开的脊状结构。 在这种结构中，互补字线或位线可以是间隔开的镶嵌特征。 镶嵌导体可以使用双图案化掩模形成，以蚀刻次光刻牺牲线，在牺牲线上形成填充物，然后去除牺牲线以留下充当填充物中镶嵌模具的沟槽。 然后用导体材料填充沟槽。 3D存储器阵列可以包括具有高K阻挡介电层的介电电荷俘获存储器单元，并且其中导体材料包括高功函数材料。