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    Method of manufacturing semiconductor device
    11.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5972741A

    公开(公告)日：1999-10-26

    申请号：US958992

    申请日：1997-10-28

    申请人： Hirotoshi Kubo ,  Eiichiroh Kuwako ,  Masanao Kitagawa ,  Masahito Onda ,  Hiroaki Saitou ,  Keita Odajima

    发明人： Hirotoshi Kubo ,  Eiichiroh Kuwako ,  Masanao Kitagawa ,  Masahito Onda ,  Hiroaki Saitou ,  Keita Odajima

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/352

    CPC分类号： H01L29/7813

    摘要： A first conductivity layer and a first insulating film are successively formed on a channel layer, and a photoresist film is formed on the first insulating film. The photoresist film is selectively exposed to light using a photomask and patterned. Using the patterned photoresist film as a mask, the first insulating film and the first conductivity layer are etched to form source electrodes from the first conductivity layer. Using the first insulating film and the source electrodes as a mask, an impurity of one conductivity type is diffused into exposed portions of the channel layer to form source regions. A second insulating film is formed in covering relation to side walls and upper surfaces of the source electrodes. Using the second insulating film as a mask, the channel layer and the common drain layer are etched to form trenches in the source regions, the channel layer, and the common drain layer. A third insulating film is formed on surfaces of the trenches, and a second conductive layer is formed as a gate electrode on the entire surface so as to fill up the trenches and cover the second insulating film.

    摘要翻译： 在沟道层上依次形成第一导电层和第一绝缘膜，在第一绝缘膜上形成光致抗蚀剂膜。 使用光掩模将光致抗蚀剂膜选择性地暴露于光并图案化。 使用图案化的光致抗蚀剂膜作为掩模，第一绝缘膜和第一导电层被蚀刻以从第一导电层形成源电极。 使用第一绝缘膜和源电极作为掩模，一种导电类型的杂质扩散到沟道层的暴露部分中以形成源极区。 形成与源极电极的侧壁和上表面相关的第二绝缘膜。 使用第二绝缘膜作为掩模，蚀刻沟道层和公共漏极层，以在源极区，沟道层和公共漏极层中形成沟槽。 第三绝缘膜形成在沟槽的表面上，并且在整个表面上形成第二导电层作为栅电极，以填充沟槽并覆盖第二绝缘膜。

    Semiconductor device and manufacturing method thereof
    12.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US20050073004A1

    公开(公告)日：2005-04-07

    申请号：US10929727

    申请日：2004-08-31

    申请人： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

    发明人： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

    IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/861

    CPC分类号： H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

    摘要： Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

    摘要翻译： 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

    Method of fabricating semiconductor device
    13.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06395604B1

    公开(公告)日：2002-05-28

    申请号：US09652013

    申请日：2000-08-31

    申请人： Hirotoshi Kubo ,  Hiroaki Saito ,  Masanao Kitagawa ,  Eiichiroh Kuwako

    发明人： Hirotoshi Kubo ,  Hiroaki Saito ,  Masanao Kitagawa ,  Eiichiroh Kuwako

    IPC分类号： H01L21336

    CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

    摘要： The present invention improves the characteristic of a trench-type vertical MOSFET. When a trench 23 serving as a gate 25 is formed, it is made in a shape of “&ggr;” which is convex toward the inside of the trench. Thus, the surface area of the trench is reduced so that both gate-source capacitance and gate-drain capacitance can be reduced, thereby shortening the switching time of the MOSFET.

    摘要翻译： 本发明改进了沟槽型垂直MOSFET的特性。 当形成用作栅极25的沟槽23时，其形成为朝向沟槽内部凸出的“γ”形状。 因此，沟槽的表面积减小，从而可以减小栅极 - 源极电容和栅极 - 漏极电容，从而缩短MOSFET的开关时间。

    Method of manufacturing semiconductor device
    16.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06967139B2

    公开(公告)日：2005-11-22

    申请号：US10893223

    申请日：2004-07-19

    申请人： Makoto Oikawa ,  Hiroki Etou ,  Hirotoshi Kubo ,  Shouji Miyahara

    发明人： Makoto Oikawa ,  Hiroki Etou ,  Hirotoshi Kubo ,  Shouji Miyahara

    IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

    摘要： In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.

    摘要翻译： 在常规功率MOSFET中，在操作区域的最外周的栅电极底部产生电场浓度，从而导致漏极与源极之间或集电极与发射极之间的高电压强度的劣化。 在本发明中，操作区域的最外周的沟槽比操作区域的沟槽浅。 由此，减轻了操作区域的最外周的栅电极底部的电场浓度，并且抑制了漏极与源极之间的高电压强度的劣化。 此外，通过使最外周沟槽开口部分变窄，可以通过相同的步骤形成深度不同的沟槽。

    Method for manufacturing semiconductor device
    17.
    发明申请
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20050255706A1

    公开(公告)日：2005-11-17

    申请号：US11123248

    申请日：2005-05-06

    申请人： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

    发明人： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

    IPC分类号： H01L21/28 ,  H01L21/30 ,  H01L21/31 ,  H01L21/322 ,  H01L21/336 ,  H01L21/469 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/74 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L21/3003 ,  H01L21/76886 ,  H01L21/823487 ,  H01L29/456

    摘要： In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

    摘要翻译： 在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。 然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。 因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。 根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。 因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。 此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

    Manufacturing method of semiconductor device
    19.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07320916B2

    公开(公告)日：2008-01-22

    申请号：US10952381

    申请日：2004-09-29

    申请人： Hirotoshi Kubo ,  Yasuhiro Igarashi ,  Masahiro Shibuya

    发明人： Hirotoshi Kubo ,  Yasuhiro Igarashi ,  Masahiro Shibuya

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/456

    摘要： When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer. By this, a specified concentration profile of the element region is kept, and the impurity concentration only in the vicinity of the surface can be raised. Accordingly, even if boron is absorbed by titanium silicide, a specified boron concentration can be kept in the element region, and the increase of contact resistance can be suppressed.

    摘要翻译： 当作为阻挡金属层的Ti与设置在硅衬底的表面上的硼的扩散区域接触时，存在硼被硅化钛吸收的问题，并且接触电阻增加。 虽然存在另外注入硼量的方法，其量等于由硅化钛吸收的硼的量，但是存在如下问题：当将硼另外注入例如p沟道型的源极区时， 在扩散步骤中另外添加硼深度扩散，特性劣化。 根据本发明，在形成元件区域之后，以元素区域的约10％的剂量将硼额外地注入整个表面，并且通过合金化工艺在硅衬底的表面附近活化 阻挡金属层。 由此，保持元件区域的规定的浓度分布，仅能够提高表面附近的杂质浓度。 因此，即使硼被硅化钛吸收，也可以在元件区域中保持规定的硼浓度，能够抑制接触电阻的增加。