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    Semiconductor device and method of manufacturing the same
    6.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060054970A1

    公开(公告)日：2006-03-16

    申请号：US11220406

    申请日：2005-09-07

    申请人： Masamichi Yanagida ,  Hirotoshi Kubo ,  Junichiro Tojo ,  Hiraoki Saito ,  Masahito Onda

    发明人： Masamichi Yanagida ,  Hirotoshi Kubo ,  Junichiro Tojo ,  Hiraoki Saito ,  Masahito Onda

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/66734

    摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.

    摘要翻译： 在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。 沟道层是不进行通过热处理的扩散的杂质注入层。 通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。 由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。 因此，沟槽变浅，因此可以减小电容。 此外，通过使外延层更薄，可以使导通电阻更低。

    Method of manufacturing semiconductor device
    7.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06967139B2

    公开(公告)日：2005-11-22

    申请号：US10893223

    申请日：2004-07-19

    申请人： Makoto Oikawa ,  Hiroki Etou ,  Hirotoshi Kubo ,  Shouji Miyahara

    发明人： Makoto Oikawa ,  Hiroki Etou ,  Hirotoshi Kubo ,  Shouji Miyahara

    IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

    摘要： In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.

    摘要翻译： 在常规功率MOSFET中，在操作区域的最外周的栅电极底部产生电场浓度，从而导致漏极与源极之间或集电极与发射极之间的高电压强度的劣化。 在本发明中，操作区域的最外周的沟槽比操作区域的沟槽浅。 由此，减轻了操作区域的最外周的栅电极底部的电场浓度，并且抑制了漏极与源极之间的高电压强度的劣化。 此外，通过使最外周沟槽开口部分变窄，可以通过相同的步骤形成深度不同的沟槽。

    Method for manufacturing semiconductor device
    8.
    发明申请
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20050255706A1

    公开(公告)日：2005-11-17

    申请号：US11123248

    申请日：2005-05-06

    申请人： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

    发明人： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

    IPC分类号： H01L21/28 ,  H01L21/30 ,  H01L21/31 ,  H01L21/322 ,  H01L21/336 ,  H01L21/469 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/74 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L21/3003 ,  H01L21/76886 ,  H01L21/823487 ,  H01L29/456

    摘要： In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

    摘要翻译： 在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。 然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。 因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。 根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。 因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。 此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

    Semiconductor device and a method of fabricating the same
    9.
    发明申请
    Semiconductor device and a method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20050266642A1

    公开(公告)日：2005-12-01

    申请号：US11194446

    申请日：2005-08-02

    申请人： Hirotoshi Kubo ,  Masanao Kitagawa ,  Masahito Onda ,  Hiroaki Saito ,  Eiichiroh Kuwako

    发明人： Hirotoshi Kubo ,  Masanao Kitagawa ,  Masahito Onda ,  Hiroaki Saito ,  Eiichiroh Kuwako

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 which is exposed through the recess, the side wall insulator 28, and the insulating film.

    摘要翻译： 功率MOSFET包括：第一导电类型的半导体衬底21; 第一导电类型的漏极层22，并形成在衬底的表面层上; 形成在漏极层22上的部分区域中的栅极绝缘膜25; 形成在栅极绝缘膜25上的栅电极26; 形成在栅电极上的绝缘膜27; 形成在栅极绝缘膜25，栅电极26和绝缘膜27的侧壁上的侧壁绝缘体28; 在漏极层22上形成的凹部和形成有栅电极25和侧壁绝缘体28的区域以外的区域; 与第一导电型相反的第二导电类型的沟道层23形成在从形成凹部的区域到形成栅电极26的区域附近的范围内; 一个导电类型的源极区24，并形成在凹槽外部的沟道层23上; 以及形成为覆盖通过凹部暴露的沟道层23，侧壁绝缘体28和绝缘膜的布线层29。