公开(公告)号：US4160991A

公开(公告)日：1979-07-10

申请号：US844769

申请日：1977-10-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/12

CPC分类号： H01L21/033 ,  H01L21/2257 ,  H01L21/76229 ,  H01L23/53271 ,  H01L29/0649 ,  H01L29/42304 ,  H01L2924/0002 ,  Y10S148/051 ,  Y10S148/122 ,  Y10S148/131

摘要： A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

摘要翻译： 描述了一种用于制造高性能双极器件的方法和所得到的具有非常小的发射极 - 基极间距的结构。 与较早的器件间隔相比，小的发射极 - 基极间距降低了基极电阻，从而提高了双极器件的性能。 该方法包括提供具有通过隔离区域彼此隔离的单晶硅区域的硅半导体本体和其中的掩埋子集电极。 在分离的单晶硅中形成基极区。 在覆盖指定为发射极和集电极到达区域的区域的硅体的表面上形成掩模。 然后通过覆盖基极区域的掩模形成掺杂的多晶硅层，并与其形成欧姆接触。 在多晶硅层上形成绝缘层。 从指定为发射极和集电极到达区域的区域中去除掩模。 然后在基极区域中形成发射极结，并且集电极通过形成为与掩埋的子集电极接触。 电触点被制成发射极和集电极。 掺杂多晶硅层是与基极区的电接触。

公开(公告)号：US4252582A

公开(公告)日：1981-02-24

申请号：US115307

申请日：1980-01-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/203 ,  H01L21/22 ,  H01L21/31

CPC分类号： H01L21/033 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S148/131 ,  Y10S148/141

摘要： A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

摘要翻译： 一种制造高性能双极晶体管的方法，其特征在于自对准发射极和基极区域以及最小的基极和发射极接触间隔。 所公开的方法包括形成具有相反导电外延层和衬底的凹陷氧化物隔离结构。 交替的氮化硅和二氧化硅层的多层质量被放置在基极区域和集电极贯通区域之上。 多晶硅沉积在台面之间。 底面蚀刻台面以暴露离子注入的外部碱性区域。 然后，去除台面以暴露发射极和本征基极区域以及集电极贯通区域。 后者的曝光区域被适当地离子注入。 触头直接连接到发射极和集电极到达区域，并间接通过多晶硅到基极区域。

公开(公告)号：US4214315A

公开(公告)日：1980-07-22

申请号：US21123

申请日：1979-03-16

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

IPC分类号： H01L21/762 ,  H01L21/8228 ,  H01L27/07 ,  H01L27/082 ,  H01L29/47 ,  H01L27/02

CPC分类号： H01L27/0826 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/82285 ,  H01L27/0766 ,  H01L29/47

摘要： A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

摘要翻译： 给出了在同一半导体器件上制造垂直NPN和PNP结构的方法。 该方法包括提供具有通过隔离区彼此隔离的单晶硅区域的单晶半导体衬底。 掩埋区域形成为与衬底和外延层的接合部重叠，并且位于分离的单晶硅的至少一个区域中。 NPN指定区域中的P基区域和PNP指定区域中的P到达通孔同时形成。 然后在NPN区域中的发射极区域和PNP区域中的基极接触区域同时形成。 然后通过合适的离子注入技术注入PNP区域中的P发射极区域。 形成PNP区域中的肖特基势垒集电极触点。 然后对PNP和NPN晶体管元件进行电触点。 如果需要，可以制造PNP器件而不形成NPN器件。

公开(公告)号：US4426655A

公开(公告)日：1984-01-17

申请号：US293413

申请日：1981-08-14

申请人： Harsaran S. Bhatia ,  David B. Eardley ,  Santosh P. Gaur

发明人： Harsaran S. Bhatia ,  David B. Eardley ,  Santosh P. Gaur

IPC分类号： G11C11/34 ,  H01L27/102 ,  H01L29/74 ,  H01L29/48

CPC分类号： H01L27/1028 ,  G11C11/34

摘要： A dynamic memory cell uses a low barrier Schottky contact at a drain region to eliminate the need for an external gating diode. The drain is separated from source and injector regions by a heavily doped N+ reach through region extending to a heavily doped N+ blanket semiconductor. Holes injected into one of the separated regions are trapped by high-low junctions and are detected by sensing the source-drain current.

摘要翻译： 动态存储单元在漏极区域使用低阻挡肖特基接触以消除对外部门控二极管的需要。 漏极通过重掺杂N +到达区域延伸到重掺杂的N +覆盖半导体与源极和注入器区域分离。 注入一个分离区域的孔被高低交点捕获，并通过感测源极 - 漏极电流来检测。

公开(公告)号：US4535531A

公开(公告)日：1985-08-20

申请号：US360730

申请日：1982-03-22

申请人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

发明人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

IPC分类号： H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82

CPC分类号： H01L27/0825 ,  H01L21/3065 ,  H01L21/8222 ,  H01L29/1004

摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.

摘要翻译： 描述了一种方法，其允许在集成电路芯片的选定区域中制造非常窄的基极宽度双极晶体管，并且在同一集成电路芯片的其它选定区域上制造宽基极宽度的双极晶体管。 将晶体管特性从集成电路芯片的一个区域选择性地变化到另一个区域的能力提供了有价值的集成电路设计的自由度。 使用常规技术将集成电路芯片上的双极晶体管加工成发射点形成点。 但是，在发射极形成之前，将使用反应离子蚀刻干法蚀刻作为具有非常窄的基极晶体管的选定区域的发射极的基极区域。 将其中具有发射极开口的现有氮化硅/二氧化硅层用作该反应离子蚀刻程序的蚀刻掩模。 一旦蚀刻完成到期望的深度，则恢复正常处理以形成发射器和金属化的其余部分。

公开(公告)号：US4746815A

公开(公告)日：1988-05-24

申请号：US881755

申请日：1986-07-03

申请人： Harsaran S. Bhatia ,  Mario E. Ecker ,  Harry J. Jones ,  Shashi D. Malaviya

发明人： Harsaran S. Bhatia ,  Mario E. Ecker ,  Harry J. Jones ,  Shashi D. Malaviya

IPC分类号： H01L21/82 ,  G06F1/22 ,  H01L21/822 ,  H01L23/538 ,  H01L27/04 ,  H03K3/26 ,  H03K3/335

CPC分类号： G06F1/22 ,  H01L23/5382 ,  H01L2924/0002 ,  Y10T307/492

摘要： A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.

摘要翻译： 一种特别设计的模块和集成电路芯片，允许在芯片接收器和驱动器电路之间共享模块EC焊盘。 该芯片具有其中每个接收器电路的直接正常输入线和来自其中每个驱动器电路的直接正常输出线以及从这些电路中的每一个到各种EC焊盘的信号线。 该芯片还包括用于在其正常和EC线路之间切换接收器电路和驱动器电路以实现电子删除功能的开关和控制电路。 在优选实施例中，大部分EC焊盘通过开关和控制电路可切换地连接到不同组的三个相邻接收器电路，驱动电路或其组合。 该设计允许使用模块通常需要的大约一半的EC焊盘，同时允许在大多数情况下同时向三个相邻的接收器或驱动器电路进行EC连接。

公开(公告)号：US4712125A

公开(公告)日：1987-12-08

申请号：US661999

申请日：1984-10-18

申请人： Harsaran S. Bhatia ,  Satyapal S. Bhatia ,  Jacob Riseman ,  Emmanuel A. Valsamakis

发明人： Harsaran S. Bhatia ,  Satyapal S. Bhatia ,  Jacob Riseman ,  Emmanuel A. Valsamakis

IPC分类号： H01L21/225 ,  H01L21/60 ,  H01L23/485 ,  H01L29/735 ,  H01L29/04

CPC分类号： H01L21/76897 ,  H01L21/225 ,  H01L23/485 ,  H01L29/735 ,  H01L2924/0002 ,  H01L2924/10158

摘要： A method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body is described. A substantially vertical conformal conductive layer is formed over the desired PN junction region. The body is heated at a suitable temperature to cause a dopant to diffuse from the vertical conductive layer into the semiconductor body to form the narrow width PN junction region. A substantially horizontal conductive layer makes contact to the substantially vertical layer so as to have the horizontal conductive layer in electrical contact to the PN junction region. Electrical contact can be made to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of very small device that can be made using the method of the present invention.

摘要翻译： 描述了在任何所需的半导体本体中与窄宽度PN结区域接触的方法和结果。 在期望的PN结区域上形成基本垂直的保形导电层。 将体在合适的温度下加热以使掺杂剂从垂直导电层扩散到半导体本体中以形成窄宽度PN结区域。 基本上水平的导电层与大致垂直的层接触，以使水平导电层与PN结区电接触。 可以在任何方便的位置对水平导电层进行电接触。 横向PNP晶体管是可以使用本发明的方法制造的一种非常小的器件。

公开(公告)号：US07704802B2

公开(公告)日：2010-04-27

申请号：US11871484

申请日：2007-10-12

申请人： Harsaran S. Bhatia ,  Eric Kline

发明人： Harsaran S. Bhatia ,  Eric Kline

IPC分类号： H01L21/84

CPC分类号： H01L27/118 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1203

摘要： Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.

摘要翻译： 公开了一种可编程随机逻辑器件阵列，以及形成这种器件的方法。 该器件包括衬底和衬底上方的半导体层。 该半导体层又包括第一半导体类型的第一区域，第二半导体类型的间隔开的第二区域阵列和多个空间电荷区域。 每个空间电荷区域围绕相应的一个第二区域延伸，并且将第二区域中的一个与半导体层的第一区域分离。 可编程随机逻辑器件阵列还包括第一组和第二组触点。 第一组触点与半导体层的所述第一区域的区域电接触，并且第二组触点与第二区域电接触。

公开(公告)号：US5427983A

公开(公告)日：1995-06-27

申请号：US997827

申请日：1992-12-29

申请人： Umar M. U. Ahmad ,  Harsaran S. Bhatia ,  Satya P. S. Bhatia ,  Hormazdyar M. Dalal ,  William H. Price ,  Sampath Purushothaman

发明人： Umar M. U. Ahmad ,  Harsaran S. Bhatia ,  Satya P. S. Bhatia ,  Hormazdyar M. Dalal ,  William H. Price ,  Sampath Purushothaman

IPC分类号： H01L21/203 ,  C23C14/04 ,  C23C28/02 ,  H01L21/48 ,  H01L21/52 ,  H01L23/12 ,  H01L23/498 ,  H05K1/09 ,  H05K3/14 ,  H05K3/24 ,  H01L21/44

CPC分类号： H01L23/49811 ,  C23C14/042 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/143 ,  H05K3/244 ,  Y10S148/105 ,  Y10T428/12528 ,  Y10T428/12743 ,  Y10T428/1275 ,  Y10T428/12806 ,  Y10T428/12819 ,  Y10T428/12861 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/12896 ,  Y10T428/12903 ,  Y10T428/1291

摘要： A thin-layer metallization structure in which the final gold layer is deposited by evaporation with the surface onto which it is evaporated maintained at an elevated temperature. By evaporating the uppermost gold layer of the structure at an elevated substrate temperature, the gold atoms have a higher mobility, causing the deposited gold to spread over the edge of the structure and cover the otherwise exposed edges, including the edge at the copper interface.

摘要翻译： 其中通过蒸发沉积最终金层的薄层金属化结构与蒸发的表面保持在升高的温度。 通过在升高的基板温度下蒸发结构的最上层的金层，金原子具有更高的迁移率，导致沉积的金铺展在结构的边缘上并且覆盖否则暴露的边缘，包括在铜界面处的边缘。

公开(公告)号：US5243140A

公开(公告)日：1993-09-07

申请号：US771707

申请日：1991-10-04

申请人： Harsaran S. Bhatia ,  Mario J. Interrante ,  Suresh D. Kadakia ,  Shashi D. Malaviya ,  Mark H. McLeod ,  Sudipta K. Ray ,  Herbert I. Stoller

发明人： Harsaran S. Bhatia ,  Mario J. Interrante ,  Suresh D. Kadakia ,  Shashi D. Malaviya ,  Mark H. McLeod ,  Sudipta K. Ray ,  Herbert I. Stoller

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/5382 ,  H01L21/485 ,  H01L2224/16225 ,  H01L2924/19107

摘要： A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.