公开(公告)号：US20170110237A1

公开(公告)日：2017-04-20

申请号：US15191203

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  Niranjan Sunil MUDAKATTE ,  Jonghae KIM ,  Chengjie ZUO ,  David Francis BERDY

IPC: H01F27/28 ,  H03H7/01 ,  H03F15/00 ,  H01F41/04

CPC classification number: H01F27/2847 ,  H01F17/0013 ,  H01F41/04 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/004 ,  H03F15/00 ,  H03H7/0138

Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

公开(公告)号：US20170372831A1

公开(公告)日：2017-12-28

申请号：US15192802

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Daeik Daniel KIM ,  Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Changhan Hobie YUN ,  Jonghae KIM ,  Chengjie ZUO ,  Yunfei MA ,  Robert Paul MIKULKA

IPC: H01F27/28 ,  H01F41/04 ,  H01L23/00

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F17/0033 ,  H01F2017/002 ,  H01L23/3128 ,  H01L23/645 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/023 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/1206 ,  H01L2924/18162 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

公开(公告)号：US20170221846A1

公开(公告)日：2017-08-03

申请号：US15077869

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  Chengjie ZUO ,  David Francis BERDY ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/15 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/14 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1148 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/145 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/0052 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09845 ,  Y02P70/611

Abstract: A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.

公开(公告)号：US20170133148A1

公开(公告)日：2017-05-11

申请号：US15345312

申请日：2016-11-07

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Changhan Hobie YUN ,  Daeik Daniel KIM ,  David Francis BERDY ,  Jonghae KIM ,  Yunfei MA ,  Chengjie ZUO

IPC: H01F27/28 ,  H01L23/00 ,  H01L21/56 ,  H01F38/14 ,  H01F27/02 ,  H01F27/29 ,  H01F41/06 ,  H01L23/31 ,  H04B5/00

CPC classification number: H01F27/2823 ,  H01F27/022 ,  H01F27/2828 ,  H01F27/29 ,  H01F38/14 ,  H01F41/06 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L28/00 ,  H01L28/10 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/08265 ,  H01L2224/16227 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19042 ,  H01L2924/19104 ,  H04B5/0037 ,  H04B5/0081 ,  H01L2224/05599 ,  H01L2924/20751 ,  H01L2224/85399

Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

公开(公告)号：US20170084565A1

公开(公告)日：2017-03-23

申请号：US14859323

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  David Francis BERDY ,  Changhan Hobie YUN ,  Jonghae KIM ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Je-Hsiung Jeffrey LAN ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0905

Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.

公开(公告)号：US20170077214A1

公开(公告)日：2017-03-16

申请号：US14853967

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil MUDAKATTE ,  Daeik Daniel KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/94 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10337 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03

Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

Abstract translation: 增强电容器结构包括基板和在基板上的第一导电层的第一电容器板。 增强电容器结构还包括在第一电容器板的远离衬底的表面上的绝缘体层和第二电容器板。 第二电容器板包括在绝缘体层上的第二导电层，由第一电容器板作为第一电容器支撑。 与第一电容器串联耦合的第二电容器。 第一电容器板由第一电容器和第二电容器共享作为共用的第一电容器板。 扩展的第一电容器板包括第三导电层的第一虚拟部分和沿着共享的第一电容器板的表面延伸的第一虚设通孔条。 第一虚拟部分沿第一虚拟通孔条延伸并由第一虚拟通孔支撑。

公开(公告)号：US20160254237A1

公开(公告)日：2016-09-01

申请号：US14634148

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  Chengjie ZUO ,  Jonghae KIM ,  Matthew Michael NOWAK

IPC: H01L23/60 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L21/568 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，该导电屏蔽立即围绕扇出晶片级封装（FOWLP）模块或器件中的各个芯片。 FOWLP模块或设备内各个芯片之间的模块内屏蔽是通过电磁或无线电信号（RF）隔离来实现的，该隔离由导体屏蔽的表面立即围绕每个芯片。 导体屏蔽层直接连接到FOWLP的一个或多个接地导体部分，以确保可靠的接地。

公开(公告)号：US20150371751A1

公开(公告)日：2015-12-24

申请号：US14313241

申请日：2014-06-24

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  David Francis BERDY ,  Jonghae KIM

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/04 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/15 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  Y10T29/49075 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Abstract translation: 方法和装置，其中所述方法在基底中形成第一多个通孔，还包括将所述第一多个通孔形成为基本上相同的高度。 该方法在衬底外部形成多个导电迹线，并将多个导电迹线耦合到第一多个通孔：其中多个导电迹线和第一多个通孔包括多个导电匝，并且其中多个导电 匝在基本上在第一平面内的螺旋构造。

公开(公告)号：US20250047310A1

公开(公告)日：2025-02-06

申请号：US18363290

申请日：2023-08-01

Applicant: QUALCOMM INCORPORATED

Inventor： Alper GENC ,  David Francis BERDY ,  Christian HOLENSTEIN ,  Jose CABANILLAS

IPC: H04B1/00

Abstract: A radio frequency (RF) switching system including a plurality of band filters comprising a first band filter a second band filter and a third band filter, the first, second and third band filters configured to process signals in different communication bands, a switch located between the first, second and third band filters and a first and a second antenna, the switch configured to selectively couple the first, second and third filters to the first and second antennas, the switch comprising at least a first switch element and a second switch element configured to receive complementary control signals, wherein at least the first and the second filter are configured to be simultaneously coupled to the first antenna and the switch is configured to delay at least one of the complementary control signals by an amount defined by a difference (delta) between an ON to OFF time (Toff) and an OFF to ON time (Ton) of the first switch element and the second switch element when the switch, in response to the complementary control signals, is configured to selectively connect the first antenna to the third filter instead of the second filter while the first filter is coupled to the first antenna and a first communication path through the first filter to the first antenna is active.

公开(公告)号：US20190259780A1

公开(公告)日：2019-08-22

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Daniel Daeik KIM ,  Matthew Michael NOWAK ,  Jonghae KIM ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  David Francis BERDY

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/306 ,  H01L23/66 ,  H01L27/088 ,  H01L21/304 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.