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公开(公告)号：US20250130739A1
公开(公告)日：2025-04-24
申请号：US18935798
申请日：2024-11-04
Applicant: Rambus Inc.
Inventor： Lei Luo , John C. Eble, III
IPC: G06F3/06
Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.
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12.发明公开公开(公告)号：US20240168873A1
公开(公告)日：2024-05-23
申请号：US18162824
申请日：2021-08-06
Applicant: Rambus Inc.
Inventor： Andrew M. Fuller , Barry William Daly , Thomas J. Giovannini , Lei Luo , Masum Hossain
IPC: G06F12/02 , G11C11/408
CPC classification number: G06F12/0223 , G11C11/4082
Abstract: Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.
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公开(公告)号：US11955161B2
公开(公告)日：2024-04-09
申请号：US18103386
申请日：2023-01-30
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lei Luo , Liji Gopalakrishnan
IPC: G06F1/04 , G06F1/08 , G06F1/3234 , G06F1/3237 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4096
CPC classification number: G11C11/4076 , G06F1/04 , G06F1/08 , G06F1/3234 , G06F1/3237 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G11C11/4087 , G11C11/4096 , Y02D10/00 , Y02D30/50
Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
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公开(公告)号：US11049546B2
公开(公告)日：2021-06-29
申请号：US16865928
申请日：2020-05-04
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lei Luo , Liji Gopalakrishnan
IPC: G11C11/4076 , G11C11/4096 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G06F1/3237 , G06F1/04 , G06F1/3234 , G06F1/08 , G11C11/408
Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
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公开(公告)号：US10541693B2
公开(公告)日：2020-01-21
申请号：US16242475
申请日：2019-01-08
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/091 , H03K5/156 , H03L7/00 , G11C7/10 , G11C7/22 , H04L7/00 , H04L7/033 , H03L7/08 , H03L7/099 , G11C7/04
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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Patent Agency Ranking
公开(公告)号：US20180196489A1
公开(公告)日：2018-07-12
申请号：US15863712
申请日：2018-01-05
Applicant: Rambus Inc.
Inventor： Yu Chang , Lei Luo , Kyung Suk Oh
CPC classification number: G06F1/3203 , H04B1/12 , H04L7/0054 , H04L7/033 , H04L25/03006 , H04L25/03012 , H04L25/03057 , H04L25/03127 , H04L25/03146 , H04L25/03853 , H04L2025/03433
Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.
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公开(公告)号：US09748960B2
公开(公告)日：2017-08-29
申请号：US14456716
申请日：2014-08-11
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/091 , H03L7/099 , H03L7/00 , G11C7/10 , G11C7/22 , H04L7/033 , H03L7/08 , H04L7/00 , G11C7/04
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US09373384B2
公开(公告)日：2016-06-21
申请号：US13845503
申请日：2013-03-18
Applicant: Rambus Inc.
Inventor： Ravindranath Kollipara , Lei Luo , Ian Shaeffer
IPC: H03K19/003 , G11C11/401 , G11C5/04 , G11C7/10
CPC classification number: G11C11/401 , G11C5/04 , G11C7/1057 , G11C7/1084
Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.
Abstract translation: 实施例涉及具有可编程输入电容的集成电路器件。 例如，存储器件的可编程寄存器可以存储代表控制引脚的输入电容值的调整值。 一个实施例旨在通过允许较轻负载的引脚的可编程性来控制同步存储器系统的偏斜，以便增加它们的负载以匹配负载较重的引脚。 通过将较轻负载的引脚匹配到负载较重的引脚，系统表现出改进的控制和地址引脚的传播延迟同步。 此外，实施例提供了根据设备上多少等级来改变负载的能力。
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公开(公告)号：US09166838B1
公开(公告)日：2015-10-20
申请号：US14489814
申请日：2014-09-18
Applicant: Rambus Inc.
Inventor： Lei Luo , Barry W. Daly , Kambiz Kaviani , John Cronan Eble, III , John Wilson
CPC classification number: H03K3/013 , G11C5/147 , G11C29/021 , G11C29/022 , G11C29/028 , H04L25/0296 , H04L25/06 , H04L25/08
Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.
Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。
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公开(公告)号：US20240282357A1
公开(公告)日：2024-08-22
申请号：US18598237
申请日：2024-03-07
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lei Luo , Liji Gopalakrishnan
IPC: G11C11/4076 , G06F1/04 , G06F1/08 , G06F1/3234 , G06F1/3237 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G11C11/408 , G11C11/4096
CPC classification number: G11C11/4076 , G06F1/04 , G06F1/08 , G06F1/3234 , G06F1/3237 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G11C11/4087 , G11C11/4096 , Y02D10/00 , Y02D30/50
Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
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