公开(公告)号：US20220013457A1

公开(公告)日：2022-01-13

申请号：US16924968

申请日：2020-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Shinichi UCHIDA

IPC: H01L23/522 ,  H01L49/02 ,  H03F3/04 ,  H03M1/12

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.

公开(公告)号：US20200168545A1

公开(公告)日：2020-05-28

申请号：US16653127

申请日：2019-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Akio ONO ,  Shinichi KUWABARA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.

公开(公告)号：US20180182751A1

公开(公告)日：2018-06-28

申请号：US15796816

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Takafumi KURAMOTO ,  Yasutaka NAKASHIBA

IPC: H01L27/06 ,  H01L27/12 ,  H01L29/93 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66174 ,  H01L29/93 ,  H01L29/94

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.

公开(公告)号：US20170186689A1

公开(公告)日：2017-06-29

申请号：US15456976

申请日：2017-03-13

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu NEMOTO ,  Yasutaka NAKASHIBA ,  Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Kazunori GO ,  Hiroshi OE ,  Noriko YOSHIKAWA

IPC: H01L23/522 ,  G01R33/06 ,  H01L23/528 ,  G01R31/26 ,  H01F27/28 ,  H01L49/02

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

公开(公告)号：US20160093570A1

公开(公告)日：2016-03-31

申请号：US14863264

申请日：2015-09-23

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE ,  Shinichi UCHIDA ,  Tadashi MAEDA ,  Kazuo HENMI

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/528 ,  H01L23/31 ,  H01L25/065 ,  H04B5/00

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.

Abstract translation: 在相对的两个半导体芯片之间防止介电击穿，以提高半导体器件的可靠性。 第一半导体芯片具有包括多个布线层的布线结构，在布线结构中形成的第一线圈和形成在布线结构上的绝缘膜。 第二半导体芯片具有包括多个布线层的布线结构，形成在布线结构上的第二线圈和形成在布线结构上的绝缘膜。 第一半导体芯片和第二半导体芯片通过绝缘片与第一半导体芯片的绝缘膜和第二半导体芯片的绝缘膜彼此面对而堆叠。 第一线圈和第二线圈彼此磁耦合。 然后，在第一和第二半导体芯片的每一个中，在最上层布线层形成布线和虚拟布线。

公开(公告)号：US20150048481A1

公开(公告)日：2015-02-19

申请号：US14527293

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Yasutaka NAKASHIBA ,  Takatsugu NEMOTO

IPC: H01L23/522

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor.An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

公开(公告)号：US20210151394A1

公开(公告)日：2021-05-20

申请号：US17095277

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA

IPC: H01L23/64 ,  H02J50/12 ,  H04B5/00 ,  H01L49/02 ,  H01L21/56

Abstract: The semiconductor device includes a first semiconductor substrate having a first surface and a second surface having a relationship with each other, a first circuit and electrically connected to the first circuit, and a first inductor formed at a position overlapping with the first semiconductor substrate, between the first surface and the first circuit, a first chip formed so as to cover the first surface, a second semiconductor substrate having a third surface and a fourth surface having a relationship with each other, a second circuit and electrically connected, and a second inductor formed so as to be electromagnetically coupled with the first inductor, the second surface, grooves are formed to reach the first insulating film, in a plan view, It is formed so as to surround the first circuit.

公开(公告)号：US20200241128A1

公开(公告)日：2020-07-30

申请号：US16737556

申请日：2020-01-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Nobuyuki MORIKOSHI ,  Tomoyuki TANAKA ,  Yoshiyuki OTA ,  Ryo YOKOTA ,  Yuji MOTODA

IPC: G01S13/89 ,  G06K9/00 ,  G01S13/06

Abstract: A device control system comprises an object detection circuit configured to detect an object around a device to be controlled, an attribute identification circuit configured to identify an attribute of the device, and a control circuit configured to control the device based on a result of the detection by the object detection circuit and the attribute of the object identified by the attribute identification circuit. According to the above embodiment, it is possible to control the device without the user being aware of it.

公开(公告)号：US20180308795A1

公开(公告)日：2018-10-25

申请号：US15953872

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA ,  Shinichi KUWABARA

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

公开(公告)号：US20170359097A1

公开(公告)日：2017-12-14

申请号：US15617738

申请日：2017-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Takafumi KURAMOTO

IPC: H04B1/44 ,  H01L23/522 ,  H04B5/00 ,  H01L23/58 ,  H01L49/02 ,  H01L23/528 ,  H03F3/213 ,  H01L23/552 ,  H01L27/06 ,  H03B5/12 ,  H03F3/195

CPC classification number: H04B1/44 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/552 ,  H01L23/585 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/10 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B2200/004 ,  H03B2200/0072 ,  H03B2201/025 ,  H03F1/565 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45731 ,  H04B5/0081

Abstract: A semiconductor device and a communication circuit capable of reducing the effect of a noise generated in an inductor are provided. A semiconductor device according to an embodiment includes a substrate, a first circuit disposed in a first area of the substrate, a second circuit disposed in a second area of the substrate, the second circuit being configured to operate selectively with the first circuit, a first inductor disposed in the second area and connected to the first circuit, and a second inductor disposed in the first area and connected to the second circuit.