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    A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
    11.
    发明申请
    A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权

    公开(公告)号：US20150341043A1

    公开(公告)日：2015-11-26

    申请号：US14817645

    申请日：2015-08-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke KIMURA ,  Yuichi OKUDA ,  Hideo NAKANE ,  Takaya YAMAMOTO

    IPC: H03M1/00 ,  H03M1/44 ,  H03M1/06

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    CURRENT GENERATION CIRCUIT, AND BANDGAP REFERENCE CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    12.
    发明申请
    CURRENT GENERATION CIRCUIT, AND BANDGAP REFERENCE CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
    电流产生电路，以及包括其的带状基准电路和半导体器件

    公开(公告)号：US20150293552A1

    公开(公告)日：2015-10-15

    申请号：US14669352

    申请日：2015-03-26

    Applicant: Renesas Electronics Corporation

    Inventor： Atsushi MOTOZAWA ,  Yuichi OKUDA

    IPC: G05F3/26

    CPC classification number: G05F3/30 ,  G05F3/245 ,  G05F3/267

    Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

    Abstract translation: 一种包括第一和第二双极晶体管的电流产生电路，使第一电流和第二电流分别通过第一和第二双极晶体管的电流分配电路分别对应于第一和第二双极晶体管的第一电流和第二电流 ，设置在所述第一双极晶体管和所述第一电流分配电路之间的第一NMOS晶体管，设置在所述第二双极晶体管和所述第一电流分配电路之间的第二NMOS晶体管，第一电阻元件，输出所述第二控制电压的第一运算放大器 根据第一NMOS晶体管的漏极电压和基准偏置电压到第一和第二NMOS晶体管的栅极;以及第二运算放大器，其根据第二NMOS晶体管的漏极电压和第二NMOS晶体管产生第一控制电压， 参考偏置电压。

    SEMICONDUCTOR DEVICE HAVING ANALOG-TO-DIGITAL CONVERTER WITH GAIN-DEPENDENT DITHERING AND COMMUNICATION APPARATUS
    13.
    发明申请
    SEMICONDUCTOR DEVICE HAVING ANALOG-TO-DIGITAL CONVERTER WITH GAIN-DEPENDENT DITHERING AND COMMUNICATION APPARATUS 有权
    具有增益依赖和通信设备的模拟数字转换器的半导体器件

    公开(公告)号：US20140022103A1

    公开(公告)日：2014-01-23

    申请号：US13940819

    申请日：2013-07-12

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke KIMURA ,  Tatsuji MATSUURA ,  Yuichi OKUDA ,  Hideo NAKANE ,  Takaya YAMAMOTO

    IPC: H03M1/20

    CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

    SEMICONDUCTOR DEVICE FOR WIRELESS COMMUNICATION
    17.
    发明申请
    SEMICONDUCTOR DEVICE FOR WIRELESS COMMUNICATION 审中-公开
    无线通信半导体器件

    公开(公告)号：US20160043712A1

    公开(公告)日：2016-02-11

    申请号：US14920015

    申请日：2015-10-22

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichi OKUDA

    IPC: H03K17/14 ,  H03K17/687 ,  H03K17/60 ,  H03K17/06

    CPC classification number: H03K17/14 ,  G06K7/10237 ,  G06K19/0705 ,  G06K19/0709 ,  H01L27/0222 ,  H01L27/088 ,  H01L27/0928 ,  H03K17/063 ,  H03K17/60 ,  H03K17/6877

    Abstract: Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors.

    Abstract translation: 提供一种无线通信的半导体装置，其能够实现泄漏功率的降低并且能够提高功率效率。 例如，对于外部端子，耦合用于驱动天线的天线驱动器部分和用于整流来自天线的输入功率的整流部分。 天线驱动器部分包括上拉PMOS晶体管和下拉式NMOS晶体管。 在整流部中，由全波整流电路产生的电源电压由升压电路升压。 例如，当停止从电池供应电源电压时，由升压电路的升压产生的电源电压被提供给每个上拉PMOS晶体管的大部分。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    18.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20150256193A1

    公开(公告)日：2015-09-10

    申请号：US14711733

    申请日：2015-05-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takashi OSHIMA ,  Tatsuji MATSUURA ,  Yuichi OKUDA ,  Hideo NAKANE ,  Takaya YAMAMOTO ,  Keisuke KIMURA

    IPC: H03M1/12 ,  H03M1/44 ,  H03M1/06 ,  H03M1/00

    CPC classification number: H03M1/1245 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

    Abstract translation: 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近，数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正， 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。

    A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
    20.
    发明申请
    A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    A / D转换器电路和半导体集成电路

    公开(公告)号：US20150188555A1

    公开(公告)日：2015-07-02

    申请号：US14579049

    申请日：2014-12-22

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke KIMURA ,  Yuichi OKUDA ,  Hideo NAKANE ,  Takaya YAMAMOTO

    IPC: H03M1/06 ,  H03M1/44 ,  H03M1/00

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    Abstract translation: 一种具有简单设计并能够防止表面积增加和其他问题的模数转换器电路。 用于将模拟输入信号转换为数字量的模数转换器电路包括将模拟输入信号转换成预校正数字值的模数转换器单元，以及对预连接进行数字校正的校正单元 从模数转换器单元输出的数字值。 校正单元包括加权系数乘法器单元，其输出通过将从每个比特提供的加权系数乘以从A / D转换器单元输出的预校正数字值的每一位并将其相加得到的校正后数字值，以及 加权系数搜索单元，其搜索加权系数，以便最小化基于校正后数字值产生的误差信号和校正后数字值的近似值。

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